Skip to content

Version 2 of the BST decoder core

Tom Levens requested to merge development into master

Both delayed and non-delayed versions of the bunch/turn clocks are available from the core. The delay value is now controlled by a WB register instead of an input port. Also, some general clean-up and port renaming for consistency.

New modules BstClkConv, BstDelay and BstRegister added to provide additional functionality in the user code.

Resolves #1 (closed)

Edited by Tom Levens

Merge request reports