Version 2 of the BST decoder core (!2) · Merge requests · bi / HDL_Cores / BST_FPGA

Tom Levens requested to merge development into master Apr 28, 2019

Both delayed and non-delayed versions of the bunch/turn clocks are available from the core. The delay value is now controlled by a WB register instead of an input port. Also, some general clean-up and port renaming for consistency.

New modules BstClkConv, BstDelay and BstRegister added to provide additional functionality in the user code.

Resolves #1 (closed)

Edited Apr 28, 2019 by Tom Levens

Version 2 of the BST decoder core

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