Correcting the Decoder

dtc-fe/firmware/hdl/AsyncCounterDecoder.vhd

@@ -329,7 +329,12 @@ begin
                     if number_boxcars_rxd = 0 then 
                        if pkg_counter > 0 then
                             async_counter_o.clk_counter <= clock_cycle_counter-1;
-                            async_counter_o.pkg_counter <= pkg_counter-1; 
+                            async_counter_o.pkg_counter <= pkg_counter-1;
+                            -- Collects the data coming in over each of the BX for 8BXs and repeats that 2040 times. Each MPA sends one counter data per 8BXs. So, since there are 8 MPAs connected to CIC2, there would be 8 counter data per 8BXs. As CIC2 output is sorted based on the bits corresponding to the bend info,
+                            -- counter data won't be in a sequence. Need to check the AX bits to know which data corresponds to which MPA at the end of accumulation. The assumption here is that the first 8 "stub data" would correspond to the counter data from 8 MPAs.
+                            -- in each BX, data is collected from L1 to L6 over 16 rows in 640MHz mode and over 8 rows for 320MHz mode. So slvs_lines_i(0)(15) (in 640MHz mode)/slvs_lines_i(0)(7)(in 320MHz mode) corresponds to bit 'C' in Figure 13 of CIC2_specs_v1p0 (MSB first logic).  
+                            -- Cross check the logic
+                            pkg_data <= boxcar_0 & boxcar_1 & boxcar_2 & boxcar_3 & boxcar_4 & boxcar_5 & boxcar_6 & boxcar_7;        
                             for counter_num in 0 to 7 loop
                                 -- inputting each of the AX bits plus parsed counter data (S10 B12 B11 B10 Z13 Z12 Z11 Z10 S17 S16 S15 S14 S13 S12 S11 - format as per the logic in slvs_debug_generic_line_fifo) into data_out. 
                                 -- to understand the parsing logic, for counter_num = 0, pkg_data((352 - (counter_num*21)) downto (352 - (counter_num*21) - 2)) would correspond to pkg_data(352 downto 350) which is [A12 A11 A10] in Figure 13 of CIC2_specs_v1p0.
@@ -339,12 +344,7 @@ begin
                                                                                                                    pkg_data((48*8-1-34 - (counter_num*21)) downto (48*8-1-34 - (counter_num*21) - 6));
                             end loop; 
                        end if;
-                    end if;
-                    -- Collects the data coming in over each of the BX for 8BXs and repeats that 2040 times. Each MPA sends one counter data per 8BXs. So, since there are 8 MPAs connected to CIC2, there would be 8 counter data per 8BXs. As CIC2 output is sorted based on the bits corresponding to the bend info,
-                    -- counter data won't be in a sequence. Need to check the AX bits to know which data corresponds to which MPA at the end of accumulation. The assumption here is that the first 8 "stub data" would correspond to the counter data from 8 MPAs.
-                    -- in each BX, data is collected from L1 to L6 over 16 rows in 640MHz mode and over 8 rows for 320MHz mode. So slvs_lines_i(0)(15) (in 640MHz mode)/slvs_lines_i(0)(7)(in 320MHz mode) corresponds to bit 'C' in Figure 13 of CIC2_specs_v1p0 (MSB first logic).  
-                    -- Cross check the logic
-                    pkg_data <= boxcar_0 & boxcar_1 & boxcar_2 & boxcar_3 & boxcar_4 & boxcar_5 & boxcar_6 & boxcar_7;                                      
+                    end if;                               
                     if boxcar_counter >= 2040 and store_fsm_state = Idle  then 
                         packing_fsm_state <= Idle;
                         async_counter_o.capture_done <= '1';