Finished formatting first pass

CODE_STYLE.md

@@ -3,7 +3,11 @@
 #### Name conventions:
 - Constants should have a `c` prefix and be in camel case
 - Types should have a `t` prefix and be in came case
+- Entity names should be in camel case, beginning with a capital letter. They should also end with `Instance` and be descriptive
+- Processes should be named, beginning with a lowercase `p` and be descriptive
+- Generate statements should be named, beginning with `gen` and be descriptive
 
 #### File structure
 - Use entities in place of components
 - Inputs and outputs of an entity should be grouped under a specific header. IPbus ports should be placed under their own header
+- Any new block should be indented relative to its parent (including architectures, generate statements, processes and if statements).

dtc-be/firmware/hdl/FormatOutput.vhd

@@ -5,42 +5,34 @@ use work.config.all;
 use work.dtc_stubs.all;
 
 entity dtc_formatOutput is
-port (
-    clk: in std_logic;
-    formatOutput_din: in t_stubsDTC( numLinksDTC - 1 downto 0 );
-    formatOutput_dout: out ldata( numLinksDTC - 1 downto 0 )
-);
+    port (
+        --- Input Ports ---
+        clk               : in std_logic;
+        formatOutput_din  : in t_stubsDTC( numLinksDTC - 1 downto 0 );
+        --- Output Ports ---
+        formatOutput_dout : out ldata( numLinksDTC - 1 downto 0 )
+    );
 end;
 
 architecture rtl of dtc_formatOutput is
-
-component dtc_formatOutput_node
-port (
-    clk: in std_logic;
-    node_din: in t_stubDTC;
-    node_dout: out lword
-);
-end component;
-
 begin
-
-g: for k in numLinksDTC - 1 downto 0 generate
-
-signal node_din: t_stubDTC := nullStub;
-signal node_dout: lword := ( ( others => '0' ), '0', '0', '1' );
-
-begin
-
-node_din <= formatOutput_din( k );
-formatOutput_dout( k ) <= node_dout;
-
-c: dtc_formatOutput_node port map ( clk, node_din, node_dout );
-
-end generate;
-
+    genFormatOutputNodes : for k in numLinksDTC - 1 downto 0 generate
+    begin
+        --==============================--
+        FormatOutputNodeInstance : entity work.dtc_formatOutput_node
+        --==============================--
+        port map (
+            --- Input Ports ---
+            clk       => clk,
+            node_din  => formatOutput_din(k),
+            --- Output Ports ---
+            node_dout => formatOutput_dout(k)
+        );
+    end generate;
 end;
 
 
+
 library ieee;
 use ieee.std_logic_1164.all;
 use work.emp_data_types.all;
@@ -51,53 +43,53 @@ use work.dtc_config.all;
 
 entity dtc_formatOutput_node is
 port (
-    clk: in std_logic;
-    node_din: in t_stubDTC;
-    node_dout: out lword
+    --- Input Ports ---
+    clk       : in std_logic;
+    node_din  : in t_stubDTC;
+    --- Input Ports ---
+    node_dout : out lword
 );
 end;
 
 architecture rtl of dtc_formatOutput_node is
 
-signal din: t_stubDTC := nullStub;
-signal dout: lword := ( ( others => '0' ), '0', '0', '1' );
-
-signal reset: std_logic := '0';
-signal counter: std_logic_vector( widthStubs - 1 downto 0 ) := ( others => '0' );
+    signal din     : t_stubDTC                                   := nullStub;
+    signal dout    : lword                                       := ( ( others => '0' ), '0', '0', '1' );
 
+    signal reset   : std_logic                                   := '0';
+    signal counter : std_logic_vector( widthStubs - 1 downto 0 ) := ( others => '0' );
 
 begin
 
-node_dout <= dout;
-din <= node_din;
-
-process ( clk ) is
-begin
-if rising_edge( clk ) then
+    node_dout <= dout;
+    din       <= node_din;
 
+    process ( clk ) is
+    begin
+        if rising_edge( clk ) then
 
-    dout.data <= ( others => '0' );
-    if dout.valid = '1' then
-        if din.valid = '1' then
-            dout.data <= conv( din );
-        end if;
-        counter <= incr( counter );
-        if uint( counter ) = numStubs - downTime - 1 then
-            dout.valid <= '0';
             dout.data <= ( others => '0' );
-        end if;
-    end if;
+            if dout.valid = '1' then
+                if din.valid = '1' then
+                    dout.data <= conv( din );
+                end if;
+                counter <= incr( counter );
+                if uint( counter ) = numStubs - downTime - 1 then
+                    dout.valid <= '0';
+                    dout.data <= ( others => '0' );
+                end if;
+            end if;
+
+            reset <= din.reset;
+            if reset = '1' then
+                dout.valid <= '1';
+                if din.valid = '1' then
+                    dout.data <= conv( din );
+                end if;
+                counter <= ( others => '0' );
+            end if;
 
-    reset <= din.reset;
-    if reset = '1' then
-        dout.valid <= '1';
-        if din.valid = '1' then
-            dout.data <= conv( din );
         end if;
-        counter <= ( others => '0' );
-    end if;
-
-end if;
-end process;
+    end process;
 
 end;

dtc-be/firmware/hdl/top.vhd

@@ -9,7 +9,7 @@ use work.dtc_config.all;
 
 entity dtc_top is
 port (
-    -- Input Ports ---
+    --- Input Ports ---
     clk      : in std_logic;
     dtc_din  : in ldata( 4 * N_REGION - 1 downto 0 );
     --- Output Ports ---
@@ -78,7 +78,7 @@ begin
         transform_din   => transform_din,
         --- Input Ports ---
         transform_dout  => transform_dout,
-        -- IPbus Ports ---
+        --- IPbus Ports ---
         transform_ipbus => transform_ipbus
     );