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Commit 10a4abf5 authored by Kirika Uchida's avatar Kirika Uchida
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update

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Stage: Static Analysis
Stage: Make Project
Stage: Pre-build Checks
Stage: Synthesis
Stage: Implementation
Stage: Package
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top/muone/firmware/hdl/emp_payload.vhd
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...@@ -113,6 +113,7 @@ architecture rtl of emp_payload is ...@@ -113,6 +113,7 @@ architecture rtl of emp_payload is
signal ecal_link_data : tDaqEcalLinkDataArray; signal ecal_link_data : tDaqEcalLinkDataArray;
signal ecal_data : ldata(cNumberOfEcalOutputLinks - 1 downto 0); signal ecal_data : ldata(cNumberOfEcalOutputLinks - 1 downto 0);
signal ttrig : lword := LWORD_NULL;
begin begin
......
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