Update top/firmware/hdl/LinkAggregatorCore.vhd

top/firmware/hdl/LinkAggregatorCore.vhd

@@ -24,7 +24,8 @@ entity LinkAggregatorCore is
         --- Debug Ports ---
         status_bits        : out std_logic_vector(15 downto 0);
         --- IPBus Ports ---
-        non_empty_counts   : out ipb_reg_v(8*N_LINKS - 1 downto 0)
+        non_empty_counts   : out ipb_reg_v(8*N_LINKS - 1 downto 0);
+        bx_valid_count_out : out ipb_reg_v(0 downto 0)
     );
 end LinkAggregatorCore;
 
@@ -131,6 +132,8 @@ architecture compressed of LinkAggregatorCore is
     signal bx_valid_array        : std_logic_vector(N_LINKS * cBoxcarBx - 1 downto 0) := (others => '0');
     
     signal non_empty_fifo_count  : ipb_reg_v(8*N_LINKS - 1 downto 0)        := (others => (others => '0'));
+    signal bx_valid_count        : ipb_reg_v(0 downto 0)                    := (others => (others => '0'));
+    signal pBx_counter           : integer                                  := 0;
 
 begin
 
@@ -194,9 +197,13 @@ begin
                         end if;
                     end if;
                     -- Check for non-empty FIFOs at reset
-                    if route_reset = '1' then
-                        if empty_route = '0' then
-                            non_empty_fifo_count(N_LINKS*j + i) <= std_logic_vector(unsigned(non_empty_fifo_count(N_LINKS*j + i)) + 1);
+                    if reset = '1' then 
+                        non_empty_fifo_count(N_LINKS*j + i) <= (others => '0');
+                    else
+                        if route_reset = '1' then
+                            if empty_route = '0' then
+                                non_empty_fifo_count(N_LINKS*j + i) <= std_logic_vector(unsigned(non_empty_fifo_count(N_LINKS*j + i)) + 1);
+                            end if;
                         end if;
                     end if;
                 end if;
@@ -295,7 +302,6 @@ begin
         -- Process to iterate of the link FIFOs and route the data to the output FIFO, if data is present on a given link.
         -- The process uses a rotating pointer to repeatedly iterate over all links, taking one stub per iteration, until all link FIFOs are empty.
         --==============================--
-        
             variable bx_valid_variable : std_logic := '0';
         
         begin
@@ -345,8 +351,10 @@ begin
                 bx_valid <= bx_valid_variable;               
                 
                 -- If counter is at the end of a packet, then start to readout the contents of the aggregated FIFOs
-                if counter = 47 and empty = '0' then
-                    rd_en <= '1';
+                if counter = 47 then
+                    if empty = '0' then
+                        rd_en <= '1';
+                    end if;
                 end if;
                 if rd_en = '1' then
                     if almost_empty = '1' then
@@ -362,6 +370,7 @@ begin
                     links_out(i).data  <= (others => '0');
                 end if;               
                 links_out(i).strobe <= '1';
+
             end if;
             
         end process pIteratePointer;
@@ -416,6 +425,40 @@ begin
         end if;
     end process pReadoutReset;
 
+    --==============================--
+    pCountValidBits : process(clk_p)
+    --==============================--
+        variable bx_valid_variable : std_logic := '0';
+    begin
+        if rising_edge(clk_p) then
+            if counter = 47 then 
+                pBx_counter <= 0;
+            else
+                if pBx_counter = 8 then
+                    pBx_counter <= pBx_counter;
+                else
+                    pBx_counter <= pBx_counter + 1;
+                end if;
+            end if;
+
+            if pBx_counter < 8 then
+                bx_valid_variable := '1';
+                for j in 0 to N_LINKS - 1 loop
+                    bx_valid_variable := bx_valid_variable and bx_valid_array(N_LINKS*pBx_counter + j);
+                end loop;
+            end if;
+
+            -- Increment counter if bx_valid is set high when readout is started
+            if reset = '1' then 
+                bx_valid_count(0) <= (others => '0');
+            else
+                if bx_valid_variable = '1' then
+                    bx_valid_count(0) <= std_logic_vector(unsigned(bx_valid_count(0)) + 1);
+                end if;
+            end if;
+        end if;
+    end process pCountValidBits
+
     --==============================--
     -- Debug
     --==============================--
@@ -430,5 +473,6 @@ begin
     status_bits(8) <= cache_overflow_array(0)(0); -- link_aggregator_cache_0_0_overflow;
     status_bits(9) <= route_overflow_array(0)(0); -- link_aggregator_route_0_0_overflow;
     non_empty_counts <= non_empty_fifo_count;
+    bx_valid_count_out <= bx_valid_count;
 
 end compressed;