Update top/firmware/hdl/LinkAggregatorCore.vhd

top/firmware/hdl/LinkAggregatorCore.vhd

@@ -128,6 +128,7 @@ architecture compressed of LinkAggregatorCore is
     signal route_overflow_array  : tEnableArray                             := cNullEnableArray;
     signal cache_overflow_array  : tEnableArray                             := cNullEnableArray;
     
+    signal bx_valid_array        : std_logic_vector(N_LINKS * cBoxcarBx - 1 downto 0) := (others => '0');
     
     signal non_empty_fifo_count  : ipb_reg_v(8*N_LINKS - 1 downto 0)        := (others => (others => '0'));
 
@@ -168,6 +169,7 @@ begin
             signal din_route, dout_route                                                              : std_logic_vector(cFIFOWidth - 1 downto 0) := (others => '0');
             signal count_route                                                                        : std_logic_vector(4 downto 0);
             signal route_reset                                                                        : std_logic                                 := '0';
+            signal countdown_iterator                                                                 : unsigned(3 downto 0)                      := (others => '0');
 
         begin
             
@@ -181,11 +183,13 @@ begin
                     if packet_start = '1' then
                         if empty_cache = '0' then
                             rd_en_cache <= '1';
+                            countdown_iterator <= unsigned(count_cache) - 1;
                         end if;
-                    end if;
-                    if rd_en_cache = '1' then
-                        -- Use almost empty flag to avoid underflow
-                        if almost_empty_cache = '1' then
+                    else
+                        if countdown_iterator > 0 then
+                            countdown_iterator <= countdown_iterator - 1;
+                        else
+                            countdown_iterator <= countdown_iterator;
                             rd_en_cache <= '0';
                         end if;
                     end if;
@@ -198,6 +202,22 @@ begin
                 end if;
             end process pTransferToRoutingFIFO;
             
+            --==============================--
+            pCheckBxValidConditionPerLink : process(clk_p)
+            --==============================--
+            begin
+                if rising_edge(clk_p) then
+                    if packet_start = '1' then
+                        if unsigned(count_cache) > 0 then
+                            bx_valid_array(N_LINKS*j + i) <= '1';
+                        else
+                            bx_valid_array(N_LINKS*j + i) <= '0';
+                        end if;
+                    end if;
+                end if;
+            end process pCheckBxValidConditionPerLink;
+            
+            
             -- Enable writing of routing FIFO using the valid flag of the cache FIFO
             wr_en_route <= valid_cache;
             din_route <= dout_cache;
@@ -267,12 +287,17 @@ begin
         signal previous_valid_row                             : std_logic_vector(N_LINKS - 1 downto 0)    := (others => '0');
         signal all_links_reset                                : std_logic                                 := '0';
         
+        signal bx_valid                                       : std_logic                                 := '0';
+
     begin
         --==============================--
         pIteratePointer : process(clk_p)
         -- Process to iterate of the link FIFOs and route the data to the output FIFO, if data is present on a given link.
         -- The process uses a rotating pointer to repeatedly iterate over all links, taking one stub per iteration, until all link FIFOs are empty.
         --==============================--
+        
+            variable bx_valid_variable : std_logic := '0';
+        
         begin
 
             if rising_edge(clk_p) then
@@ -312,6 +337,12 @@ begin
                     wr_en <= '0';
                 end if;
                 
+                -- Check if Bx is valid
+                bx_valid_variable := '1';
+                for j in 0 to N_LINKS - 1 loop
+                    bx_valid_variable := bx_valid_variable and bx_valid_array(N_LINKS*i + j);
+                end loop;
+                bx_valid <= bx_valid_variable;               
                 
                 -- If counter is at the end of a packet, then start to readout the contents of the aggregated FIFOs
                 if counter = 47 and empty = '0' then