Fixed signal naming

common/firmware/hdl/PayloadHeaderGenerator.vhd

@@ -21,7 +21,7 @@ entity PayloadHeaderGenerator is
         --- Ouput Ports ---
         header_out : out tPayloadHeaderArray := (others => (others => '0'));
         --- Debug Ports ---
-        super_id : out std_logic_vector(31 downto 0) := (others => '0')
+        debug_super_id : out std_logic_vector(31 downto 0) := (others => '0')
     );
 end PayloadHeaderGenerator;
 
@@ -104,5 +104,6 @@ begin
 
     end generate ; -- genOutput
     
+    debug_super_id <= super_id;
 
 end Behavioral;