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Commit 83f93a0a authored by David Gabriel Monk's avatar David Gabriel Monk
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Merge branch 'add-histogram-enable' into 'master'

Add histogram enable bit

See merge request !17
parents de6db33d e16931f7
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1 merge request!17Add histogram enable bit
Pipeline #4297132 passed
--- ---
sources: sources:
emp-fwk: emp-fwk:
branch: master commit: b84d1324
url: https://gitlab.cern.ch/p2-xware/firmware/emp-fwk.git url: https://gitlab.cern.ch/p2-xware/firmware/emp-fwk.git
ttc_legacy: ttc_legacy:
......
...@@ -7,7 +7,8 @@ ...@@ -7,7 +7,8 @@
<node id="csr" address="0x00004" description="Histogram control and status" fwinfo="endpoint;width=2"> <node id="csr" address="0x00004" description="Histogram control and status" fwinfo="endpoint;width=2">
<node id="windowL" address="0x0"/> <node id="windowL" address="0x0"/>
<node id="windowH" address="0x1" mask="0x000f"/> <node id="windowH" address="0x1" mask="0x000f"/>
<node id="histogram_sel" address="0x1" mask="0xfff0"/> <node id="histogram_enable" address="0x1" mask="0x0010"/>
<node id="histogram_sel" address="0x1" mask="0xffe0"/>
<node id="histogram0" address="0x2"/> <node id="histogram0" address="0x2"/>
<node id="histogram1" address="0x3"/> <node id="histogram1" address="0x3"/>
</node> </node>
......
...@@ -84,6 +84,7 @@ signal max_value0, max_value1 : std_logic_vector(bin_width - 1 downto 0) := (ot ...@@ -84,6 +84,7 @@ signal max_value0, max_value1 : std_logic_vector(bin_width - 1 downto 0) := (ot
signal histogram_reset : std_logic := '0'; signal histogram_reset : std_logic := '0';
signal hist0_stub, hist1_stub : lword := LWORD_NULL; signal hist0_stub, hist1_stub : lword := LWORD_NULL;
signal histogram_sel : integer := 0; signal histogram_sel : integer := 0;
signal histogram_enable : std_logic := '0';
type tHeaderStartArray is array(cNumberOfFEModules - 1 downto 0) of std_logic_vector(1 downto 0); type tHeaderStartArray is array(cNumberOfFEModules - 1 downto 0) of std_logic_vector(1 downto 0);
signal header_start_array : tHeaderStartArray := (others => (others => '0')); signal header_start_array : tHeaderStartArray := (others => (others => '0'));
signal aggregated_stubs : ldata(7 downto 0) := (others => LWORD_NULL); signal aggregated_stubs : ldata(7 downto 0) := (others => LWORD_NULL);
...@@ -257,7 +258,8 @@ status_registers(1)(bin_width - 1 downto 0) <= max_value1; ...@@ -257,7 +258,8 @@ status_registers(1)(bin_width - 1 downto 0) <= max_value1;
trigger_window_lower <= control_registers(0); trigger_window_lower <= control_registers(0);
trigger_window_upper <= control_registers(1)(3 downto 0); trigger_window_upper <= control_registers(1)(3 downto 0);
histogram_sel <= to_integer(unsigned(control_registers(1)(15 downto 4))); histogram_enable <= control_registers(1)(4);
histogram_sel <= to_integer(unsigned(control_registers(1)(15 downto 5)));
trigger_window <= trigger_window_upper & trigger_window_lower; trigger_window <= trigger_window_upper & trigger_window_lower;
...@@ -280,7 +282,7 @@ pHistogram: process(clk_p) ...@@ -280,7 +282,7 @@ pHistogram: process(clk_p)
--==============================-- --==============================--
begin begin
if rising_edge(clk_p) then if rising_edge(clk_p) then
if stubs(histogram_sel).valid = '1' then if stubs(histogram_sel).valid = '1' and histogram_enable = '1' then
if stubs(histogram_sel).data(46) = '0' then if stubs(histogram_sel).data(46) = '0' then
hist0_stub <= stubs(histogram_sel); hist0_stub <= stubs(histogram_sel);
hist1_stub <= LWORD_NULL; hist1_stub <= LWORD_NULL;
......
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