Merge branch 'new-dtc' into 'master'

Integrate recent changes into MProcessor

See merge request !32

.gitignore

+*.code-workspace
\ No newline at end of file

.gitlab-ci.yml

@@ -3,7 +3,7 @@ include:
     file: "/ci/templates/vivado-jobs.yml"
 
 variables:
-  VIVADO_VER: "2020.2"
+  VIVADO_VER: "2022.2"
   PROJECT_DEPFILE: top.dep
   PROJECT_ALGORITHM: top
   PROJECT_NAME: mprocessor

top/addr_table/link_aggregator.xml → common/addr_table/link_aggregator.xml

@@ -3,6 +3,10 @@
     <node id="control" address="0x001" fwinfo="endpoint;width=0">
         <node id="input_link_mask" mask="0x03f"/>
         <node id="reset" mask="0x40"/>
+        <node id="trigger_threshold" mask="0x780"/>
+    </node>
+    <node id="rate_monitoring" address="0x004" fwinfo="endpoint;width=2">
+        <node id="bx_valid_count" address="0x0"/>
     </node>
     <node id="monitoring" address="0x008" fwinfo="endpoint;width=3">
         <node id="non_empty_count_0" address="0x0"/>

top/addr_table/mprocessor.xml → common/addr_table/mprocessor.xml

@@ -10,8 +10,9 @@
         <node id="header_user_bits" address="0x1"/>
     </node>
     
-    <node id="csr" address="0x22" description="MProcessor control and status" fwinfo="endpoint;width=1">
+    <node id="csr" address="0x24" description="MProcessor control and status" fwinfo="endpoint;width=2">
         <node id="header_start_select" address="0x0" mask="0x7"/>
-        <node id="lff" address="0x1" mask="0x0001"/>
+        <node id="lff" address="0x2" mask="0x0001"/>
+        <node id="super_id" address="0x3"/>
     </node>
 </node>

common/firmware/cfg/module.dep

+setup -f --cd ../cfg settings.tcl
+
+src fixed_pkg_2008.vhd
+
+src mprocessor_constants.vhd
+
+src MProcessor.vhd
+src LinkAggregatorCore.vhd
+src LinkAggregatorIPBus.vhd
+src LinkCombinerCore.vhd
+src LinkCombinerIPBus.vhd
+src --vhdl2008 TrackReconstructor.vhd
+
+src ipbus_decode_link_aggregator.vhd
+src ipbus_decode_mprocessor.vhd
+
+addrtab -t mprocessor.xml
+addrtab -t link_aggregator.xml
+
+# IP Cores
+src --cd ../cgn link_agg_single_link_fifo.xci
+setup -f --cd ../cgn link_agg_single_link_fifo.tcl
+
+src --cd ../cgn link_agg_single_link_fifo_fwft.xci
+setup -f --cd ../cgn link_agg_single_link_fifo_fwft.tcl
+
+src --cd ../cgn link_agg_all_links_fifo.xci
+setup -f --cd ../cgn link_agg_all_links_fifo.tcl
+
+src --cd ../cgn link_combin_buffer.xci
+setup -f --cd ../cgn link_combin_buffer.tcl
\ No newline at end of file

top/firmware/hdl/LinkAggregatorCore.vhd → common/firmware/hdl/LinkAggregatorCore.vhd

@@ -17,6 +17,7 @@ entity LinkAggregatorCore is
         reset              : in std_logic;
         packet_start       : in std_logic;
         links_in           : in ldata(N_LINKS - 1 downto 0);
+        trigger_threshold  : in integer := 0;
         --- Output Ports ---
         links_out          : out ldata(7 downto 0) := (others => LWORD_NULL);
         uncompressed_stubs : out ldata(N_LINKS * 8 - 1 downto 0) := (others => LWORD_NULL);
@@ -24,7 +25,8 @@ entity LinkAggregatorCore is
         --- Debug Ports ---
         status_bits        : out std_logic_vector(15 downto 0);
         --- IPBus Ports ---
-        non_empty_counts   : out ipb_reg_v(8*N_LINKS - 1 downto 0)
+        non_empty_counts   : out ipb_reg_v(8*N_LINKS - 1 downto 0);
+        bx_valid_count_out : out ipb_reg_v(0 downto 0)
     );
 end LinkAggregatorCore;
 
@@ -127,9 +129,12 @@ architecture compressed of LinkAggregatorCore is
     signal output_overflow_array : std_logic_vector(cBoxcarBx - 1 downto 0) := (others => '0');
     signal route_overflow_array  : tEnableArray                             := cNullEnableArray;
     signal cache_overflow_array  : tEnableArray                             := cNullEnableArray;
-
+    
+    signal bx_valid_array        : std_logic_vector(N_LINKS * cBoxcarBx - 1 downto 0) := (others => '0');
     
     signal non_empty_fifo_count  : ipb_reg_v(8*N_LINKS - 1 downto 0)        := (others => (others => '0'));
+    signal bx_valid_count        : ipb_reg_v(0 downto 0)                    := (others => (others => '0'));
+    signal pBx_counter           : integer                                  := 0;
 
 begin
 
@@ -168,6 +173,7 @@ begin
             signal din_route, dout_route                                                              : std_logic_vector(cFIFOWidth - 1 downto 0) := (others => '0');
             signal count_route                                                                        : std_logic_vector(4 downto 0);
             signal route_reset                                                                        : std_logic                                 := '0';
+            signal countdown_iterator                                                                 : unsigned(3 downto 0)                      := (others => '0');
 
         begin
             
@@ -181,23 +187,45 @@ begin
                     if packet_start = '1' then
                         if empty_cache = '0' then
                             rd_en_cache <= '1';
+                            countdown_iterator <= unsigned(count_cache) - 1;
                         end if;
-                    end if;
-                    if rd_en_cache = '1' then
-                        -- Use almost empty flag to avoid underflow
-                        if almost_empty_cache = '1' then
+                    else
+                        if countdown_iterator > 0 then
+                            countdown_iterator <= countdown_iterator - 1;
+                        else
+                            countdown_iterator <= countdown_iterator;
                             rd_en_cache <= '0';
                         end if;
                     end if;
                     -- Check for non-empty FIFOs at reset
-                    if route_reset = '1' then
-                        if empty_route = '0' then
-                            non_empty_fifo_count(N_LINKS*j + i) <= std_logic_vector(unsigned(non_empty_fifo_count(N_LINKS*j + i)) + 1);
+                    if reset = '1' then 
+                        non_empty_fifo_count(N_LINKS*j + i) <= (others => '0');
+                    else
+                        if route_reset = '1' then
+                            if empty_route = '0' then
+                                non_empty_fifo_count(N_LINKS*j + i) <= std_logic_vector(unsigned(non_empty_fifo_count(N_LINKS*j + i)) + 1);
+                            end if;
                         end if;
                     end if;
                 end if;
             end process pTransferToRoutingFIFO;
             
+            --==============================--
+            pCheckBxValidConditionPerLink : process(clk_p)
+            --==============================--
+            begin
+                if rising_edge(clk_p) then
+                    if packet_start = '1' then
+                        if unsigned(count_cache) >= trigger_threshold then
+                            bx_valid_array(N_LINKS*j + i) <= '1';
+                        else
+                            bx_valid_array(N_LINKS*j + i) <= '0';
+                        end if;
+                    end if;
+                end if;
+            end process pCheckBxValidConditionPerLink;
+            
+            
             -- Enable writing of routing FIFO using the valid flag of the cache FIFO
             wr_en_route <= valid_cache;
             din_route <= dout_cache;
@@ -266,6 +294,8 @@ begin
         signal compressed_stub_pointer                        : integer range 0 to 1                      := 0;
         signal previous_valid_row                             : std_logic_vector(N_LINKS - 1 downto 0)    := (others => '0');
         signal all_links_reset                                : std_logic                                 := '0';
+        
+        signal bx_valid                                       : std_logic                                 := '0';
 
     begin
         --==============================--
@@ -273,6 +303,8 @@ begin
         -- Process to iterate of the link FIFOs and route the data to the output FIFO, if data is present on a given link.
         -- The process uses a rotating pointer to repeatedly iterate over all links, taking one stub per iteration, until all link FIFOs are empty.
         --==============================--
+            variable bx_valid_variable : std_logic := '0';
+        
         begin
 
             if rising_edge(clk_p) then
@@ -312,10 +344,18 @@ begin
                     wr_en <= '0';
                 end if;
                 
+                -- Check if Bx is valid
+                bx_valid_variable := '1';
+                for j in 0 to N_LINKS - 1 loop
+                    bx_valid_variable := bx_valid_variable and bx_valid_array(N_LINKS*i + j);
+                end loop;
+                bx_valid <= bx_valid_variable;               
                 
                 -- If counter is at the end of a packet, then start to readout the contents of the aggregated FIFOs
-                if counter = 47 and empty = '0' then
-                    rd_en <= '1';
+                if counter = 47 then
+                    if empty = '0' and bx_valid = '1' then
+                        rd_en <= '1';
+                    end if;
                 end if;
                 if rd_en = '1' then
                     if almost_empty = '1' then
@@ -331,6 +371,7 @@ begin
                     links_out(i).data  <= (others => '0');
                 end if;               
                 links_out(i).strobe <= '1';
+
             end if;
             
         end process pIteratePointer;
@@ -385,6 +426,40 @@ begin
         end if;
     end process pReadoutReset;
 
+    --==============================--
+    pCountValidBits : process(clk_p)
+    --==============================--
+        variable bx_valid_variable : std_logic := '0';
+    begin
+        if rising_edge(clk_p) then
+            if counter = 47 then 
+                pBx_counter <= 0;
+            else
+                if pBx_counter = 8 then
+                    pBx_counter <= pBx_counter;
+                else
+                    pBx_counter <= pBx_counter + 1;
+                end if;
+            end if;
+
+            if pBx_counter < 8 then
+                bx_valid_variable := '1';
+                for j in 0 to N_LINKS - 1 loop
+                    bx_valid_variable := bx_valid_variable and bx_valid_array(N_LINKS*pBx_counter + j);
+                end loop;
+            end if;
+
+            -- Increment counter if bx_valid is set high when readout is started
+            if reset = '1' then 
+                bx_valid_count(0) <= (others => '0');
+            else
+                if bx_valid_variable = '1' and pBx_counter < 8 then
+                    bx_valid_count(0) <= std_logic_vector(unsigned(bx_valid_count(0)) + 1);
+                end if;
+            end if;
+        end if;
+    end process pCountValidBits;
+
     --==============================--
     -- Debug
     --==============================--
@@ -399,5 +474,6 @@ begin
     status_bits(8) <= cache_overflow_array(0)(0); -- link_aggregator_cache_0_0_overflow;
     status_bits(9) <= route_overflow_array(0)(0); -- link_aggregator_route_0_0_overflow;
     non_empty_counts <= non_empty_fifo_count;
+    bx_valid_count_out <= bx_valid_count;
 
 end compressed;

top/firmware/hdl/LinkAggregatorIPBus.vhd → common/firmware/hdl/LinkAggregatorIPBus.vhd

@@ -38,11 +38,13 @@ architecture Behavorial of LinkAggregatorIPBus is
     signal channel_sel             : ipb_reg_v(0 downto 0);
     signal ipb_chain               : ipbdc_bus_array(8 downto 0);
 
-    -- signal link_aggregator_status_registers        : ipb_reg_v(4 - 1 downto 0) := (others => (others => '0'));
-    signal control_registers : ipb_reg_v(1 - 1 downto 0)  := (others => (others => '0'));
-    signal mprocessor_monitoring_registers : ipb_reg_v(8*N_LINKS - 1 downto 0) := (others => (others => '0'));
+    -- signal link_aggregator_status_registers : ipb_reg_v(4 - 1 downto 0) := (others => (others => '0'));
+    signal control_registers                : ipb_reg_v(1 - 1 downto 0)         := (others => (others => '0'));
+    signal mprocessor_monitoring_registers  : ipb_reg_v(8*N_LINKS - 1 downto 0) := (others => (others => '0'));
+    signal rate_monitoring_registers        : ipb_reg_v(1 - 1 downto 0)         := (others => (others => '0'));
+    signal bx_valid_count                   : ipb_reg_v(1 - 1 downto 0)         := (others => (others => '0'));
 
-    signal masked_links : ldata(N_LINKS - 1 downto 0) := (others => LWORD_NULL);
+    signal masked_links                     : ldata(N_LINKS - 1 downto 0)       := (others => LWORD_NULL);
 
 begin
 
@@ -96,6 +98,21 @@ begin
         q            => control_registers
     );
 
+    --==============================--
+    RateMonitoringInstance: entity work.ipbus_ctrlreg_v
+    --==============================--
+    generic map(
+        N_CTRL       => 0,
+        N_STAT       => 1
+    )
+    port map(
+        clk          => ipb_clk,
+        reset        => ipb_rst,
+        ipbus_in     => ipb_to_slaves(N_SLV_RATE_MONITORING),
+        ipbus_out    => ipb_from_slaves(N_SLV_RATE_MONITORING),
+        d            => rate_monitoring_registers
+    );
+
     --==============================--
     channel_select: entity work.ipbus_dc_fabric_sel
     --==============================--
@@ -182,13 +199,16 @@ begin
         reset            => control_registers(0)(N_LINKS + 1 - 1),
         packet_start     => packet_start,
         links_in         => masked_links,
+        trigger_threshold => to_integer(unsigned(control_registers(0)(N_LINKS + 5 - 1 downto N_LINKS + 1))),
         --- Output Ports ---
         links_out        => links_out,
         readout_reset    => readout_reset,
         --- Debug Ports ---
         -- status_bits      => link_aggregator_status_registers(3)(15 downto 0),
-        non_empty_counts => mprocessor_monitoring_registers
+        non_empty_counts => mprocessor_monitoring_registers,
+        bx_valid_count_out => bx_valid_count
     );
     
+    rate_monitoring_registers(0) <= bx_valid_count(0);
 
 end Behavorial;

top/firmware/hdl/LinkCombinerIPBus.vhd → common/firmware/hdl/LinkCombinerIPBus.vhd

@@ -25,13 +25,16 @@ entity LinkCombinerIPBus is
         packet_start     : in std_logic;
         header_in        : in tCICHeaderArray(cNumberOfFEModules * cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
         lff              : in std_logic;
+        output_srst      : in std_logic := '0';
         --- Ouput Ports ---
         link_out         : out lword := LWORD_NULL;
         --- IPBus Ports ---
         ipb_clk          : in  std_logic;
         ipb_rst          : in  std_logic;
         ipb_in           : in  ipb_wbus;
-        ipb_out          : out ipb_rbus
+        ipb_out          : out ipb_rbus;
+        --- Debug Ports ---
+        super_id         : out std_logic_vector(31 downto 0)
     );
 end LinkCombinerIPBus;
 
@@ -44,6 +47,7 @@ architecture Behavioral of LinkCombinerIPBus is
     signal masked_input          : ldata(8 - 1 downto 0)                  := (others => LWORD_NULL);
 
     signal control_registers : ipb_reg_v(2 - 1 downto 0)  := (others => (others => '0'));
+    signal output_reset      : std_logic := '0';
 
 begin
 
@@ -88,6 +92,7 @@ begin
     begin
         if rising_edge(clk_p) then
             link_combiner_rd_en <= not lff and control_registers(0)(N_INPUT_LINKS + 2 - 1);
+            output_reset        <= control_registers(0)(N_INPUT_LINKS + 1 - 1) or output_srst;
         end if;
     end process pReadEnable;
 
@@ -101,17 +106,17 @@ begin
         --- Input Ports ---
         clk_p            => clk_p,
         reset            => reset,
-        output_reset     => control_registers(0)(N_INPUT_LINKS + 1 - 1),
+        output_reset     => output_reset,
         output_enable    => link_combiner_rd_en,
         links_in         => masked_input,
         packet_start     => packet_start,
         header_in        => header_in,
         header_user_bits => control_registers(1),
         --- Output Ports ---
-        link_out         => link_out
+        link_out         => link_out,
         --- Debug Ports ---
         -- debug            => link_combiner_debug,
-        -- debug_super_id   => link_combiner_debug_super_id,
+        debug_super_id   => super_id
         -- debug_fifo       => link_aggregator_status_registers(2)
     );
 

top/firmware/hdl/MProcessor.vhd → common/firmware/hdl/MProcessor.vhd

@@ -27,6 +27,7 @@ entity MProcessor is
         header_in          : in  tCICHeaderArray(cNumberOfFEModules * cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
         header_start_array : in  tHeaderStartArray                                                := (others => (others => '0'));
         gbe_backpressure   : in  std_logic                                                        := '0';
+        srst               : in  std_logic                                                        := '0';
         --- Output Ports ---
         link_out           : out lword                                                            := LWORD_NULL;
         --- IPBus Ports ---
@@ -48,9 +49,11 @@ architecture Behavorial of MProcessor is
     signal aggregated_stubs        : ldata(7 downto 0)           := (others => LWORD_NULL);
     signal link_aggregator_input   : ldata(N_LINKS - 1 downto 0) := (others => LWORD_NULL);
 
-    signal status_registers        : ipb_reg_v(1 - 1 downto 0)   := (others => (others => '0'));
+    signal status_registers        : ipb_reg_v(2 - 1 downto 0)   := (others => (others => '0'));
     signal control_registers       : ipb_reg_v(1 - 1 downto 0)   := (others => (others => '0'));
 
+    signal super_id                : std_logic_vector(31 downto 0) := (others => '0');
+
 begin
 
     --==============================--
@@ -78,7 +81,7 @@ begin
     --==============================--
     generic map(
         N_CTRL    => 1,
-        N_STAT    => 1
+        N_STAT    => 2
     )
     port map(
         clk       => ipb_clk,
@@ -124,13 +127,16 @@ begin
         packet_start  => packet_start,
         header_in     => header_in,
         lff           => gbe_backpressure,
+        output_srst   => srst,
         --- Output Ports ---
         link_out      => link_out,
         --- IPBus Ports ---
         ipb_clk       => ipb_clk,
         ipb_rst       => ipb_rst,
         ipb_in        => ipb_to_slaves(N_SLV_LINK_COMBINER),
-        ipb_out       => ipb_from_slaves(N_SLV_LINK_COMBINER)
+        ipb_out       => ipb_from_slaves(N_SLV_LINK_COMBINER),
+        --- Debug Ports ---
+        super_id      => super_id
     );
 
     -- --==============================--
@@ -145,6 +151,7 @@ begin
     link_aggregator_input(N_LINKS - 1 downto 0) <= links_in;
 
     status_registers(0)(0) <= gbe_backpressure;
+    status_registers(1)    <= super_id;
     packet_start           <= header_start_array(to_integer(unsigned(control_registers(0)(2 downto 0))))(0);
 
 end Behavorial;