Revert "added a buffer at ZSF"

common/addr_table/eprocessor.xml

 <node description="EcalDataProcessor Control and Status" fwinfo="endpoint">
   <node id="DP" address="0x0" description="DataProcessor control and status" fwinfo="endpoint;width=1">   
     <node id="ctrl" address="0x0" description="control registers">
-      <node id="reset" mask="0x1" description="reset"/>
-      <node id="latency" mask="0x3fe" description="latency"/>
+      <node id="reset"           mask="0x1" description="reset"/>
+      <node id="latency"         mask="0x3fe" description="latency"/>
       <node id="trig_lat_offset" mask="0x7fc00" description="trigger latency offset"/>
     </node>
     <node id="stat" address="0x1" description="status">
-      <node id="latency" mask="0x1ff" description="latency"/>
+      <node id="latency"         mask="0x1ff" description="latency"/>
       <node id="trig_lat_offset" mask="0x3fe00" description="latency"/>
+      <node id="backpressure"    mask="0x40000" description="backpressure"/>
     </node>
   </node>
   <node id="dfilter"  address="0x40"  description="Data filter control and status" fwinfo="endpoint;width=6">
 		 <node id="bypass" address="0x0" mask="0x1" description="bypass zs filter logic"/>
+		 <node id="bypass_prescale" address="0x0" mask="0x1fffe" description="bypass trigger prescale"/>
 		 <node id="zs_sc" address="0x1" mode="block" size="32" description="zs filter registers"/>
   </node>
-    <node id="mon" address="0x80" description="Ecal data monitoring" fwinfo="endpoint;width=2"/>
 </node>

common/firmware/cfg/module.dep

@@ -34,6 +34,7 @@ addrtab -t eprocessor.xml
 addrtab -t link_aggregator.xml
 addrtab -t track_finder.xml
 
+
 # IP Cores
 src --cd ../cgn link_agg_single_link_fifo.xci
 setup -f --cd ../cgn link_agg_single_link_fifo.tcl

common/firmware/hdl/EcalDataAggregator.vhd

@@ -28,6 +28,10 @@ architecture rtl of EcalDataAggregator is
   signal ecal_data_p                 : std_logic_vector(28 * 16 -1 downto 0);
   alias padding_p                    is ecal_data(ecal_data'high downto ecal_data'high-2);
   
+  signal data_out_s                  : std_logic_vector(28 * 16 -1 downto 0) := (others => '0');
+  signal data_out_s_start            : std_logic := '0'; 
+  signal data_out_s_last             : std_logic := '0';
+
   signal sync                        : std_logic := '0';
   
   type tBcIdPipe is array (integer range 0 to 8) of std_logic_vector(11 downto 0);
@@ -67,14 +71,19 @@ begin
             bcid_p(i+1) <= bcid_p(i);
           end loop;
                            
+					-- data_out pipeline
+					data_out <= data_out_s;
+          data_out_start <= data_out_s_start;
+          data_out_last <= data_out_s_last;
+
           -- capturing frames
-          data_out_start <= '0';
-          data_out_last <= '0';
+          data_out_s_start <= '0';
+          data_out_s_last <= '0';
           if sync = '0' then
              if padding_p = "111" and (unsigned(bcid_p(0)) = unsigned(bcid_p(8)) + 1 or (unsigned(bcid_p(0)) = 0 and unsigned(bcid_p(8)) = 3563) ) then
                timer := 0;
-               data_out <= ecal_data_p;
-               data_out_start <= '1';
+               data_out_s <= ecal_data_p;
+               data_out_s_start <= '1';
                last_valid_bcid <= bcid_p(0);
                sync <= '1';
              elsif timer = 7 then
@@ -86,8 +95,8 @@ begin
             if timer = 7 then
               timer := 0;
               if padding_p = "111" and (unsigned(bcid_p(0)) = unsigned(bcid_p(8)) + 1 or (unsigned(bcid_p(0)) = 0 and unsigned(bcid_p(8)) = 3563) ) then
-                data_out <= ecal_data_p;
-                data_out_start <= '1'; 
+                data_out_s <= ecal_data_p;
+                data_out_s_start <= '1'; 
                 last_valid_bcid <= bcid_p(0);
               else
                 sync <= '0';
@@ -95,7 +104,7 @@ begin
             else 
                timer := timer + 1;
                if timer = 7 then
-                 data_out_last <= '1';
+                 data_out_s_last <= '1';
                end if;
             end if;
           end if;

common/firmware/hdl/EcalDataDecoder.vhd

@@ -25,6 +25,10 @@ architecture rtl of EcalDataDecoder is
       constant ElinkDataArray_NULL : tElinkDataArray := (others => (others => '0'));
       
       signal elink_data : tElinkDataArray := ElinkDataArray_NULL;
+
+			type elink_to_lword_type is array(integer range 0 to 13) of integer;
+			constant elink_to_lword : elink_to_lword_type := (3,2,1,6,0,4,5,32+3,32+2,32+1,32+6,32+0,32+4,32+5);
+
 begin
 
   decoder: process (clk_p)
@@ -32,11 +36,9 @@ begin
   begin
     if rising_edge(clk_p) then
        
-        for j in 0 to 1 loop
-            for i in 0 to 6 loop 
-                elink_data(j*7+i) <= elink_data(j*7+i)(6 downto 0) & data_in.data(j*32+i);
-            end loop;
-        end loop;
+	    for i in 0 to 13 loop 
+ 	    	elink_data(i) <= elink_data(i)(6 downto 0) & data_in.data(elink_to_lword(i));
+      end loop;
         
     end if;
 

common/firmware/hdl/EcalDataFilter.vhd

@@ -16,7 +16,7 @@ port (
         clk_p            : in  std_logic;
         clk40            : in  std_logic;
         reset            : in  std_logic;
-        data_in_valid    : in  std_logic;
+        data_in_start    : in  std_logic;
         data_in          : in  std_logic_vector(28 * 16 -1 downto 0);
         --- Output Ports ---
         trig_o_lat       : out std_logic_vector(5 downto 0);
@@ -35,9 +35,11 @@ architecture rtl of EcalDataFilter is
   signal regs              : ipb_reg_v(32 downto 0) := (others => (others => '0'));
 
   signal bypass_s          : std_logic;
+	signal bypass_prescale_s : std_logic_vector(15 downto 0);
+  signal b_trg             : std_logic;
+	signal b_counter         : std_logic_vector(15 downto 0);
 
-  signal data_meta         : std_logic_vector(28 * 16 -1 downto 0);
-  signal data_sync         : std_logic_vector(28 * 16 -1 downto 0);
+  signal data_s            : std_logic_vector(28 * 16 -1 downto 0);
 
   signal trig_meta         : std_logic_vector(31 downto 0);
   signal trig_sync         : std_logic_vector(31 downto 0);
@@ -73,24 +75,55 @@ begin
   );
 
   bypass_s <= regs(0)(0);
+  bypass_prescale_s <= regs(0)(16 downto 1);
   zs_sc_regs_gen : for i in 0 to 31 generate
     zs_sc_regs(i) <= regs(i+1);
   end generate;
 
   trig_o_lat <= zs_valid_lat when bypass_s = '0' else "000011";
-  trig_o     <= trig_sync    when bypass_s = '0' else x"c0000001";
+  trig_o     <= trig40       when bypass_s = '0' else b_trg & b_trg & "00" & x"000000" & "000" & b_trg;
 
-  data_meta   <= data_in   when rising_edge(clk40);
-  data_sync   <= data_meta when rising_edge(clk40);
-  
-  trig_meta    <= trig40    when rising_edge(clk_p);
-  trig_sync    <= trig_meta when rising_edge(clk_p);
+  -- trig_o     <= trig_sync    when bypass_s = '0' else x"c0000001";
+
+  --data_in_proc : process(clk_p)
+	--	variable timer : integer range 0 to 7 := 0;
+  --begin
+	--	if rising_edge(clk_p) then
+
+	--		if data_in_start = '1' then
+	--			timer := 0;
+	--		elsif timer = 3 then
+	--			data_s <= data_in;
+	--		end if;
+
+	--		if timer < 7 then
+	--			timer := timer + 1;
+	--		else
+	--			timer := 0;
+	--		end if;
+
+	--	end if;
+	--end process;
+
+  --trig_meta   <= trig40      when rising_edge(clk_p);
+  --trig_sync   <= trig_meta   when rising_edge(clk_p);
   
   trig40_proc : process(clk40)
   begin
    if reset = '1' then
      trig40 <= (others => '0');
+		 b_counter <= (others => '0');
    elsif rising_edge(clk40) then
+
+		 data_s <= data_in;
+
+		 b_counter <= std_logic_vector(unsigned(b_counter) + 1);
+		 b_trg <= '0';
+		 if b_counter = std_logic_vector(unsigned(bypass_prescale_s) - 1) then
+			 b_trg <= '1';
+			 b_counter <= (others => '0');
+	   end if;
+
      zs_valid_p(0) <= zs_valid;
      zs_valid_p(1) <= zs_valid_p(0);
      zs_all_valids_p0 <= zs_all_valids;
@@ -112,7 +145,7 @@ begin
   port map (
     clk                => clk40,
     rst                => reset,
-    lpgbt_payload_i    => data_sync,
+    lpgbt_payload_i    => data_s,
     sc_regs_i          => zs_sc_regs,
     valid_o            => zs_valid,
     all_valids_o       => zs_all_valids,

common/firmware/hdl/EcalDataProcessor.vhd

@@ -62,6 +62,7 @@ architecture rtl of EcalDataProcessor is
   signal trig_ram_addrb    : std_logic_vector(5 downto 0);
   signal trig_ram_doutb    : std_logic_vector(31 DOWNTO 0);
   
+	signal trig_ram_doutb_l  : std_logic_vector(31 DOWNTO 0);
   
   signal trig_ram_enb_p      : std_logic_vector(1 downto 0);
   signal trig_valid_p      : std_logic_vector(2 downto 0);
@@ -115,10 +116,11 @@ begin
   latency <= ctrl_regs(0)(9 downto 1);
   trig_lat_offset <= ctrl_regs(0)(18 downto 10);
   stat_regs(0)(8 downto 0) <= latency;
-  stat_regs(0)(9) <= data_ready_i;
-  stat_regs(0)(10) <= d_waddr_valid_i;
-  stat_regs(0)(11) <= t_waddr_valid_i;
-  stat_regs(0)(12) <= raddr_valid_i;
+  stat_regs(0)(17 downto 9) <= trig_lat_offset;
+  stat_regs(0)(18) <= gbe_backpressure;
+  --  stat_regs(0)(10) <= d_waddr_valid_i;
+  -- stat_regs(0)(11) <= t_waddr_valid_i;
+  -- stat_regs(0)(12) <= raddr_valid_i;
   -- stat_regs(0)(13) <= zsf_bypass;
  -- stat_regs(0)(17) <= trig_ram_dina(0);
  -- stat_regs(0)(18) <= trig_ram_doutb(0);
@@ -144,7 +146,7 @@ begin
     clk_p              => clk_p,
     clk40              => clk40,
     reset              => reset,
-    data_in_valid      => data_start,
+    data_in_start      => data_start,
     data_in            => data,
     trig_o_lat         => trig_lat,
     trig_o             => trig,
@@ -201,8 +203,11 @@ begin
   ); 
   
   bp: process(clk_p)
+		constant FMAX  : integer := 255;
+		variable fsize : integer := 0;
   begin
         if reset = '1' then
+					fsize := 0;
           data_out(0).data  <= (others => '0');
           data_out(0).valid <= '0';
           data_out(0).start <= '0';
@@ -218,14 +223,30 @@ begin
           data_out(0).strobe <= '0';
           case ostate is
             when wait_start =>
-              if data_out_s.start = '1' then
+							fsize := 0;
+              if data_out_s.start = '1' and data_out_s.valid = '1' then
+								fsize := 1;
                 data_out(0).start <= data_out_s.start;
                 data_out(0).valid <= data_out_s.valid;
                 ostate <= wait_last;
+							else
+								ostate <= wait_start;
               end if;
             when wait_last =>
                 data_out(0).valid <= data_out_s.valid;
-                if data_out_s.last = '1' then
+								fsize := fsize + 1;
+								if data_out_s.valid = '0' or fsize = FMAX then
+                  data_out(0).valid <= '1';
+                  data_out(0).last <= '1';
+                  data_out(0).strobe <= '1';
+          				data_out(0).data  <= (others => '1');
+                  if gbe_backpressure = '0' then 
+                    ostate <= wait_start; 
+                  else
+                    ostate <= wait_bpoff;
+                  end if;
+                elsif data_out_s.last = '1' then
+                  data_out(0).valid <= data_out_s.valid;
                   data_out(0).last <= data_out_s.last;
                   data_out(0).strobe <= data_out_s.strobe;
                   if gbe_backpressure = '0' then 
@@ -329,7 +350,6 @@ begin
             if t_waddr_valid then
               trig_ram_wea   <= '1';
               trig_ram_addra <= std_logic_vector(to_unsigned(t_waddr,6));
-              trig_ram_dina  <= trig;
             end if;
           end if;  
  
@@ -344,15 +364,58 @@ begin
             
             data_out_s.data  <= data_ram_doutb(63 downto 0);
             if data_ram_doutb(bit_start) = '1' then
-              data_out_s.data(63 downto 32) <= trig;
+              data_out_s.data(63 downto 32) <= trig_ram_doutb;
+							trig_ram_doutb_l              <= trig_ram_doutb;
+              data_out_s.start <= trig_ram_doutb(31);
+              data_out_s.valid <= trig_ram_doutb(0) and data_ram_doutb(bit_valid);           
+						else
+              data_out_s.valid <= trig_ram_doutb_l(0) and data_ram_doutb(bit_valid);           
+              data_out_s.last  <= trig_ram_doutb_l(30) and data_ram_doutb(bit_last);
+              data_out_s.strobe <= trig_ram_doutb_l(30) and data_ram_doutb(bit_last);         
             end if;
-
-            data_out_s.valid <= trig_ram_doutb(0) and data_ram_doutb(bit_valid);           
-            data_out_s.start <= trig_ram_doutb(31) and data_ram_doutb(bit_start) and gbe_backpressure;
-            data_out_s.last  <= trig_ram_doutb(30) and data_ram_doutb(bit_last);
-            data_out_s.strobe <= trig_ram_doutb(30) and data_ram_doutb(bit_last);         
           end if;
           
+          -- data to write                   
+          data_ram_dina(63 downto 0) <= (others => '0');
+          data_ram_dina(bit_valid) <= '0';
+          data_ram_dina(bit_start) <= '0';
+          data_ram_dina(bit_last)  <= '0';
+          if data_start = '1' then
+            if data_ready = false then
+              g_timer := 0;
+              data_ready := true;
+            end if;
+            -- data frame 0 , timer 7
+            data_ram_dina(31 downto 0) <= data(data'high - 16 downto data'high - 16 - 31); -- oc? super id?
+            data_ram_dina(bit_valid) <= '1';
+            data_ram_dina(bit_start) <= '1';
+            -- data frame 0
+           f_timer := 0;
+          else
+            if f_timer = 7 then
+              f_timer := 7;
+            else
+              -- data frame 1 - 7, timer 0 - 6
+              if f_timer = 0 then
+                data_ram_dina(63 downto 32) <= data(data'high - 16 downto data'high - 16 - 31); -- calib
+                data_ram_dina(31 downto 16) <= data(data'high - 48 downto data'high - 48 - 15); -- channel 24
+                data_ram_dina(12) <= data(data'high - 3); -- spill
+                data_ram_dina(11 downto 0) <=  data(data'high - 4 downto data'high - 4 - 11); -- bcid
+              elsif f_timer < 7 then
+                data_ram_dina(63 downto 0) <= data(64*(7-f_timer)-1 downto 64*(6-f_timer));
+              end if;
+              data_ram_dina(bit_valid) <= '1';
+              f_timer := f_timer + 1;
+              if f_timer = 7 then
+                data_ram_dina(bit_last) <= '1';
+              end if;
+              -- data frame 1 - 7
+            end if; -- f_timer 
+          end if; -- data_valid
+
+          -- trigger to write 
+          trig_ram_dina  <= trig;
+
           -- data ram write address counters
           if data_ready then
             if d_waddr_valid = false then
@@ -415,45 +478,6 @@ begin
             g_timer := g_timer + 1;
           end if;
             
-          -- data to write                   
-          data_ram_addra <= std_logic_vector(to_unsigned(d_waddr, 9));
-          data_ram_dina(63 downto 0) <= (others => '0');
-          data_ram_dina(bit_valid) <= '0';
-          data_ram_dina(bit_start) <= '0';
-          data_ram_dina(bit_last)  <= '0';
-          if data_start = '1' then
-            if data_ready = false then
-              g_timer := 0;
-              data_ready := true;
-            end if;
-            -- data frame 0
-            data_ram_dina(31 downto 0) <= data(data'high - 16 downto data'high - 16 - 31); -- oc? super id?
-            data_ram_dina(bit_valid) <= '1';
-            data_ram_dina(bit_start) <= '1';
-            -- data frame 0
-           f_timer := 0;
-          else
-            if f_timer = 7 then
-              f_timer := 7;
-            else
-              -- data frame 1 - 7
-              if f_timer = 0 then
-                data_ram_dina(63 downto 32) <= data(data'high - 16 downto data'high - 16 - 31); -- calib
-                data_ram_dina(31 downto 16) <= data(data'high - 48 downto data'high - 48 - 15); -- channel 24
-                data_ram_dina(12) <= data(data'high - 3); -- spill
-                data_ram_dina(11 downto 0) <=  data(data'high - 4 downto data'high - 4 - 11); -- bcid
-              elsif f_timer < 7 then
-                data_ram_dina(63 downto 0) <= data(64*(7-f_timer)-1 downto 64*(6-f_timer));
-              end if;
-              data_ram_dina(bit_valid) <= '1';
-              f_timer := f_timer + 1;
-              if f_timer = 7 then
-                data_ram_dina(bit_last) <= '1';
-              end if;
-              -- data frame 1 - 7
-            end if; -- f_timer 
-          end if; -- data_valid
-          
         end if;   
     end process;
     

common/firmware/hdl/EcalZeroSuppressionFilter.vhd

@@ -359,10 +359,12 @@ p_SM_com_comb:process(State_com, trg, Cnt_com) is
           CONDITION := Cnt_com.bfrvld<b_MAX-Nsmpl_b;
           if CONDITION then
             BuildNextState_com(CNT_BFR, NextState_com, Cnt_com, NxtCnt_com, vld);                 
-          elsif (not(CONDITION) and not(trg='0' or en_adv='0')) then
-            BuildNextState_com(TRG_ASSRTD, NextState_com, Cnt_com, NxtCnt_com, vld);                 
-          elsif (not(CONDITION) and    (trg='0' or en_adv='0')) then
+          elsif not(CONDITION) then
             BuildNextState_com(CNT_AFTR_TRG, NextState_com, Cnt_com, NxtCnt_com, vld);                 
+--          elsif (not(CONDITION) and not(trg='0' or en_adv='0')) then
+--            BuildNextState_com(TRG_ASSRTD, NextState_com, Cnt_com, NxtCnt_com, vld);                 
+--          elsif (not(CONDITION) and    (trg='0' or en_adv='0')) then
+--            BuildNextState_com(CNT_AFTR_TRG, NextState_com, Cnt_com, NxtCnt_com, vld);                 
           else
             REPORT LF & "FAULT CONDITION in process 'p_SM_com_comb' with State_com='" & t_State_com'IMAGE(State_com) &",....)" & LF SEVERITY FAILURE;
             BuildNextState_com(WAIT_TRG, NextState_com, Cnt_com, NxtCnt_com, vld);                 

common/firmware/ucf/eprocessor_constraints.tcl

+#fast to slow
+set_multicycle_path 3 -setup -from [get_pins {payload/EcalDataProcessorInstance/EcalDataAggregatorInstance/data_out_reg[*]/C}] 
+set_multicycle_path 2 -hold -from [get_pins {payload/EcalDataProcessorInstance/EcalDataAggregatorInstance/data_out_reg[*]/C}] 
+

top/firmware/hdl/emp_payload.vhd

@@ -469,7 +469,7 @@ begin
     
 
 
-    gbe_q <= eth_link_out;
+    gbe_q(cNumberOfMProcessors-1 downto 0) <= eth_link_out(cNumberOfMProcessors-1 downto 0);
     q(5) <= eth_link_out(0);
     q(6) <= eth_link_out(1);
 

top/firmware/hdl/emp_project_decl.vhd

@@ -34,9 +34,9 @@ package emp_project_decl is
 
   -- mgt -> buf -> fmt -> (algo) -> (fmt) -> buf -> mgt -> clk -> altclk
   constant REGION_CONF : region_conf_array_t := (
---    0  => (lpgbt, buf, no_fmt, buf, lpgbt),   --Bank 225 -- Right Column
+  --  0  => (no_mgt, buf, no_fmt, buf, no_mgt),   --Bank 225 -- Right Column
     1  => (no_mgt, buf, no_fmt, buf, no_mgt),   --Bank 226
-    2  => (lpgbt, buf, no_fmt, buf, lpgbt),   --Bank 227
+  --  2  => (lpgbt, buf, no_fmt, buf, lpgbt),   --Bank 227
     3  => (lpgbt, buf, no_fmt, buf, lpgbt),   --Bank 228
     4  => (lpgbt, buf, no_fmt, buf, lpgbt),   --Bank 229
     5  => (lpgbt, buf, no_fmt, buf, lpgbt),   --Bank 230
@@ -62,6 +62,12 @@ package emp_project_decl is
   constant REGION_DATA_FRAMER_CONF : region_data_framer_conf_array_t := (
 --    2 => ( 0=>(false, true, 0, false, lpgbtv0), 1=>(false, true, 0, false, lpgbtv0), 2=>(false, true, 0, false, lpgbtv1), 3=>(false, true, 0, false, lpgbtv0)),
 --    3 => ( 0=>(false, true, 0, false, lpgbtv0), 1=>(false, true, 0, false, lpgbtv0), 2=>(false, true, 0, false, lpgbtv0), 3=>(false, true, 0, false, lpgbtv0)),
+    3 => ( 
+      0=>(false, true, 0, false, lpgbtv0),
+      1=>(false, true, 0, false, lpgbtv0),
+      2=>(false, true, 0, false, lpgbtv0),
+      3=>(false, true, 0, false, lpgbtv0)
+    ),
     4 => ( 
       0=>(false, true, 0, false, lpgbtv0),
       1=>(false, true, 0, false, lpgbtv0),
@@ -86,7 +92,7 @@ package emp_project_decl is
   -- for lpgbt
   constant REGION_LPGBT_CONF : region_lpgbt_conf_array_t := (
 --    2  => (FEC5, DATARATE_5G12, PCS),
---    3  => (FEC5, DATARATE_5G12, PCS),
+    3  => (FEC5, DATARATE_5G12, PCS),
     4  => (FEC5, DATARATE_5G12, PCS),
     5  => (FEC5, DATARATE_5G12, PCS),
     6  => (FEC5, DATARATE_5G12, PCS),