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Commit e3e5f33b authored by David Gabriel Monk's avatar David Gabriel Monk
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Merge branch 'configurable-thresholds' into 'heterogeneous-dtc' 

Added configurable threshold for each input link

See merge request !35
parents 4dd40b0f 092d3e0c
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2 merge requests!35Added configurable threshold for each input link,!34Add functionality for multiple module types in a single image
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common/addr_table/link_aggregator.xml
+ 19
− 4
View file @ e3e5f33b
<node description="Link Aggregator control and status" fwinfo="endpoint">
<node id="chan_sel" address="0x000" description="Bx channel select" fwinfo="endpoint;width=0"/>
<node id="control" address="0x001" fwinfo="endpoint;width=0">
<node id="input_link_mask" mask="0x03f"/>
<node id="reset" mask="0x40"/>
<node id="trigger_threshold" mask="0x780"/>
<node id="control" address="0x002" fwinfo="endpoint;width=1">
<node id="control_l" address="0x0">
<node id="input_link_mask" mask="0x03f"/>
<node id="reset" mask="0x40"/>
<node id="trigger_threshold_l_0" mask="0x00000780"/>
<node id="trigger_threshold_l_1" mask="0x00007800"/>
<node id="trigger_threshold_l_2" mask="0x00078000"/>
<node id="trigger_threshold_l_3" mask="0x00780000"/>
<node id="trigger_threshold_l_4" mask="0x07800000"/>
<node id="trigger_threshold_l_5" mask="0x78000000"/>
</node>
<node id="control_u" address="0x1">
<node id="trigger_threshold_u_0" mask="0x0000000f"/>
<node id="trigger_threshold_u_1" mask="0x000000f0"/>
<node id="trigger_threshold_u_2" mask="0x00000f00"/>
<node id="trigger_threshold_u_3" mask="0x0000f000"/>
<node id="trigger_threshold_u_4" mask="0x000f0000"/>
<node id="trigger_threshold_u_5" mask="0x00f00000"/>
</node>
</node>
<node id="rate_monitoring" address="0x004" fwinfo="endpoint;width=2">
<node id="bx_valid_count" address="0x0"/>
......
common/firmware/cfg/module.dep
+ 1
− 0
View file @ e3e5f33b
......@@ -10,6 +10,7 @@ src LinkAggregatorIPBus.vhd
src LinkCombinerCore.vhd
src LinkCombinerIPBus.vhd
src --vhdl2008 TrackReconstructor.vhd
src mprocessor_data_types.vhd
src PayloadHeaderGenerator.vhd
src ipbus_decode_link_aggregator.vhd
......
common/firmware/hdl/LinkAggregatorCore.vhd
+ 5
− 3
View file @ e3e5f33b
......@@ -6,6 +6,7 @@ use work.emp_data_types.all;
use work.ipbus.all;
use work.ipbus_reg_types.all;
use work.mprocessor_data_types.all;
entity LinkAggregatorCore is
......@@ -19,7 +20,8 @@ entity LinkAggregatorCore is
reset : in std_logic;
packet_start : in std_logic;
links_in : in ldata(N_LINKS - 1 downto 0);
trigger_threshold : in integer := 0;
thresholds_l : in tIntegerArray := (others => 0);
thresholds_u : in tIntegerArray := (others => 0);
--- Output Ports ---
links_out : out ldata(7 downto 0) := (others => LWORD_NULL);
uncompressed_stubs : out ldata(N_LINKS * 8 - 1 downto 0) := (others => LWORD_NULL);
......@@ -230,7 +232,7 @@ begin
begin
if rising_edge(clk_p) then
if packet_start_buffered = '1' then
if unsigned(count_cache) >= trigger_threshold then
if unsigned(count_cache) >= thresholds_l(i) and (unsigned(count_cache) <= thresholds_u(i) or thresholds_u(i) < thresholds_l(i)) then
bx_valid_array(N_LINKS*j + i) <= '1';
else
bx_valid_array(N_LINKS*j + i) <= '0';
......@@ -295,7 +297,7 @@ begin
--==============================--
genAggregatedFIFOs : for i in 7 downto 0 generate
genAggregatedFIFOs : for i in cBoxcarBx - 1 downto 0 generate
-- Generate the output FIFO instances, one per Bx, as well as the logic to route the stubs from the link FIFOs to the output.
--==============================--
signal pointer : integer := 0;
......
common/firmware/hdl/LinkAggregatorIPBus.vhd
+ 15
− 4
View file @ e3e5f33b
......@@ -5,6 +5,7 @@ use work.emp_data_types.all;
use work.ipbus.all;
use work.ipbus_reg_types.all;
use work.mprocessor_data_types.all;
use work.ipbus_decode_link_aggregator.all;
......@@ -40,12 +41,14 @@ architecture Behavorial of LinkAggregatorIPBus is
signal ipb_chain : ipbdc_bus_array(8 downto 0);
-- signal link_aggregator_status_registers : ipb_reg_v(4 - 1 downto 0) := (others => (others => '0'));
signal control_registers : ipb_reg_v(1 - 1 downto 0) := (others => (others => '0'));
signal control_registers : ipb_reg_v(1 downto 0) := (others => (others => '0'));
signal mprocessor_monitoring_registers : ipb_reg_v(8*N_LINKS - 1 downto 0) := (others => (others => '0'));
signal rate_monitoring_registers : ipb_reg_v(1 - 1 downto 0) := (others => (others => '0'));
signal bx_valid_count : ipb_reg_v(1 - 1 downto 0) := (others => (others => '0'));
signal masked_links : ldata(N_LINKS - 1 downto 0) := (others => LWORD_NULL);
signal thresholds_l : tIntegerArray := (others => 0);
signal thresholds_u : tIntegerArray := (others => 0);
begin
......@@ -87,7 +90,7 @@ begin
ControlInstance: entity work.ipbus_ctrlreg_v
--==============================--
generic map(
N_CTRL => 1,
N_CTRL => 2,
N_STAT => 0
)
port map(
......@@ -188,6 +191,13 @@ begin
end generate gMonitoringRegisters;
genThresholds: for i in 0 to N_LINKS - 1 generate
begin
thresholds_l(i) <= to_integer(unsigned(control_registers(0)(4*(i+1) - 1 + 7 downto 4*i + 7)));
thresholds_u(i) <= to_integer(unsigned(control_registers(1)(4*(i+1) - 1 downto 4*i)));
end generate;
--==============================--
LinkAggregatorInstance: entity work.LinkAggregatorCore
--==============================--
......@@ -198,10 +208,11 @@ begin
port map (
--- Input Ports ---
clk_p => clk_p,
reset => control_registers(0)(N_LINKS + 1 - 1),
reset => control_registers(0)(6),
packet_start => packet_start,
links_in => masked_links,
trigger_threshold => to_integer(unsigned(control_registers(0)(N_LINKS + 5 - 1 downto N_LINKS + 1))),
thresholds_l => thresholds_l,
thresholds_u => thresholds_u,
--- Output Ports ---
links_out => links_out,
readout_reset => readout_reset,
......
common/firmware/hdl/mprocessor_data_types.vhd 0 → 100644
+ 15
− 0
View file @ e3e5f33b
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mprocessor_data_types is
type tIntegerArray is array(0 to 5) of integer;
end package mprocessor_data_types;
package body mprocessor_data_types is
end mprocessor_data_types;
\ No newline at end of file
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