added a buffer for the data as well

common/firmware/hdl/EcalDataAggregator.vhd

@@ -23,6 +23,7 @@ architecture rtl of EcalDataAggregator is
   alias header                       is ecal_data(ecal_data'high downto ecal_data'high-3);
   alias bcid                         is ecal_data(ecal_data'high-4 downto ecal_data'high-4-11);
 
+  signal ecal_data_p                 : std_logic_vector(28 * 16 -1 downto 0);
   signal ecal_data_reg               : std_logic_vector(28 * 16 -1 downto 0);
   signal valid_reg                   : std_logic := '0';
   
@@ -56,6 +57,7 @@ begin
     begin
         if rising_edge(clk_p) then
           
+          ecal_data_p <=  ecal_data;
           bcid_p(0) <= bcid;
           for i in 0 to 7 loop
             bcid_p(i+1) <= bcid_p(i);
@@ -80,7 +82,7 @@ begin
                     
          if unsigned(bcid_p(0)) = unsigned(bcid_p(8)) + 1 or (unsigned(bcid_p(0)) = 0 and unsigned(bcid_p(8)) = 3563) then
             timer := 0;
-            ecal_data_reg <= ecal_data;
+            ecal_data_reg <= ecal_data_p;
             valid_reg <= '1';
           elsif timer = 7 then
             timer :=0;