Add a gempy-based reg.py interface
Description
This MR adds a reg.py
interface running on the back-end board based on gempy
and thus using the LMDB address table directly.
Related Issue
This MR implements #134 (closed) in the command line.
How Has This Been Tested?
Reading and write registers are possible on the GE1/1 integration setup CTP7 using
$ ssh -t gempro@gem-shelf01-amc02 'bash -l -c "bin/reg.py"'
gempro@gem-shelf01-amc02's password:
(Cmd) read_all TTC*PHASE
GEM_AMC.TTC.CTRL.DISABLE_PHASE_ALIGNMENT 0x00000000
GEM_AMC.TTC.CTRL.LOCKMON_TARGET_PHASE 0x00001000
GEM_AMC.TTC.CTRL.PHASEMON_JUMP_THRESH 0x00000aeb
GEM_AMC.TTC.CTRL.PHASEMON_LOG2_N_AVG 0x00000005
GEM_AMC.TTC.CTRL.PHASEMON_MMCM_RESET ERROR
GEM_AMC.TTC.CTRL.PHASE_ALIGNMENT_RESET ERROR
GEM_AMC.TTC.STATUS.CLK.PHASEMON_MMCM_LOCKED 0x00000001
GEM_AMC.TTC.STATUS.CLK.PHASE_LOCKED 0x00000000
GEM_AMC.TTC.STATUS.CLK.PHASE_MONITOR ERROR
GEM_AMC.TTC.STATUS.CLK.PHASE_MONITOR.PHASE 0x00000115
GEM_AMC.TTC.STATUS.CLK.PHASE_MONITOR.PHASE_JUMP_CNT 0x00000000
GEM_AMC.TTC.STATUS.CLK.PHASE_MONITOR.PHASE_MAX 0x00000126
GEM_AMC.TTC.STATUS.CLK.PHASE_MONITOR.PHASE_MIN 0x000000fa
GEM_AMC.TTC.STATUS.CLK.PHASE_MONITOR.SAMPLE_COUNTER 0x0000b7f4
GEM_AMC.TTC.STATUS.CLK.PHASE_UNLOCK_CNT 0x00000002
GEM_AMC.TTC.STATUS.CLK.PHASE_UNLOCK_TIME 0x0000075d
(Cmd) write GEM_AMC.TTC.CTRL.LOCKMON_TARGET_PHASE 0x999
(Cmd) read GEM_AMC.TTC.CTRL.LOCKMON_TARGET_PHASE
GEM_AMC.TTC.CTRL.LOCKMON_TARGET_PHASE 0x00000999
(Cmd)
Types of changes
-
Bug fix (non-breaking change which fixes an issue) -
New feature (non-breaking change which adds functionality) -
Breaking change (fix or feature that would cause existing functionality to change)
Checklist:
-
My code follows the code style of this project. -
My change requires a change to the documentation. -
I have updated the documentation accordingly. -
I have read the CONTRIBUTING document. -
I have added tests to cover my changes. -
All new and existing tests passed.
Edited by Laurent Petre