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A simple piece of VHDL that will generate some 8b10b encoded packages for the HGTD altiroc emulator https://gitlab.cern.ch/atlas-hgtd/hgtd-peb/-/blob/master/Demonstration/module%20emulator%20v2/module_emulator_v2.pdf
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Module for adding timestamp information into the data stream.
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Petalinux configuration and binaries for the reference implementation of the White Rabbit PTP Core (https://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core)
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The package features the Placet interfaced with Python and the class extending its functionality
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Ola Slettevoll Groettvik / UVVM_All
MIT LicenseOpen Source VHDL Verification Component Framework for making structured VHDL testbenches for verification of FPGA and ASIC.
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Web interface to verify FELIX boards based on Versal chip
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