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HDL cores library of the BE-BI group

Boreal Caribou Firmware

BST implementation for FPGA

The BTrain-over-WhiteRabbit project provides a set of IP cores that implement a transport layer to be used for transmission of BTrain-related information over WR network. See project wiki

IP for Caribou Peary firmware: Data FIFO with AXI interface to CPU

HW IP core for controlling the pulser on the CaR board over an AXI bus

The second implementation of CBC3 backend firmware and the software interface. Intended to be optimized for wafer testing system.

RTL and verification code of the CLICpix2 chip.

CMS HGCROC chip common testbench FW repo

CMS HGCROC chip common testbench FW repo