Explore projects
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The BTrain-over-WhiteRabbit project provides a set of IP cores that implement a transport layer to be used for transmission of BTrain-related information over WR network. See project wiki
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The BTrain-over-WhiteRabbit project provides a set of IP cores that implement a transport layer to be used for transmission of BTrain-related information over WR network. See project wiki
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IP for Caribou Peary firmware: Data FIFO with AXI interface to CPU
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HW IP core for controlling the pulser on the CaR board over an AXI bus
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The second implementation of CBC3 backend firmware and the software interface. Intended to be optimized for wafer testing system.
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BE-CEM-EDL / Common / cheby
GNU General Public License v3.0 or laterUpdated -
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CLICdp / ASICs / CLICpix2
GNU General Public License v3.0 onlyRTL and verification code of the CLICpix2 chip.
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CMS HGCROC chip common testbench FW repo
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tmrg / cocotb_fault_injection
GNU General Public License v3.0 onlyFault injection into RTL and Netlist designs using cocotb!
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Sources, scripts and generated ip-cores. https://github.com/fpgasystems/davos https://github.com/fpgasystems/fpga-network-stack/
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This is a project with the documentation, firmware and software for the ATLAS Tile Calorimeter read-out link and control board, namely the DaughterBoard.
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