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perfectly working project

RTL and verification code of the CLICpix2 chip.

Module for adding timestamp information into the data stream.

HW IP core for controlling the pulser on the CaR board over an AXI bus

IP for Caribou Peary firmware: Data FIFO with AXI interface to CPU

Interface to ADC on CaR Board v1.x, component AD9249

Peary Caribou DAQ firmware

Interface to ADC on CaR Board v1.x, component AD9249

Control for CaR board pulsers

VFC-HD related files of the S-GEFE (L-GEFE + C-GEFE) test project

S-GEFE related files of the S-GEFE (L-GEFE + C-GEFE) test project