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[FS] FELIX Firmware

HDL on Git

DAQ and test system for the RD53 readout chips

GBT-SC for FPGA: This module (VHDL) allows performing slow-control of the front-end through GBT links (GBTx and SCA configuration)

One Repository to rule them all

Firmware dedicated to the communication with the GBTx ASIC

LpGBT-FPGA example design targeting the KCU105 platform.

Timing Compensated Link

CMS HGCROC chip common testbench FW repo

VFC-HD system core

HDL cores library of the BE-BI group

Wrapper code to integrate the particle flow HLS code into mp7fw.

Example design: implementation of the LpGBT-FPGA in a simulation testbench

Modules for the instantiation of the DDR3 of the VFC-HD board

Firmware for the PBv3 mass tester active board.

VFC-HD base project

The Dirac Extension for the linear collider related detector studies in the ILC VO