Added a "ready" output signal for the TX side of the SCA core

This merge request adds a "ready" output signal that indicates whether the SCA core is ready to accept a new command request. This allows one to provide a sequence of slow control commands from a FIFO. The FIFO will then only be popped when the previous command has been completed.

This code has been tested at Baylor U in a Zynq FPGA talking to a GBT-SCA chip on a GBT-SCA mezzanine board built by U Minnesota.