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Commit 2d47bd6d authored by Marcos Vinicius Silva Oliveira's avatar Marcos Vinicius Silva Oliveira
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added mux vhdl

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rpt/extract_info.py
+ 1
− 1
View file @ 2d47bd6d
......@@ -2,7 +2,7 @@ import glob
import re
import csv
basepaths = glob.glob('../syn/prj*')
basepaths = glob.glob('../syn/*')
basepaths.sort()
extract_info = []
......
rpt/report.csv
+ 94
− 0
View file @ 2d47bd6d
Implementation,LUTs,FFs,Logic Levels,LL-1,LL+1,High Fanout,HF-1,HF+1,Routes,Routes-1,Routes+1,Requirement,Req-1,Req+1,Path Delay,PD-1,PD+1,Slack,Slack-1,Slack+1,Logic Delay,LD-1,LD+1,Net Delay,ND-1,ND+1
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../syn/prj_I016_O016_D000,5911,0,47,0,0,42,4,1,47,1,1,6.250,6.250,6.250,19.215,1.435,0.482,-12.884,4.646,5.411,5.319(28%),0.094(7%),0.096(20%),13.896(72%),1.341(93%),0.386(80%)
../syn/ret_I016_O016_D000,5911,0,47,0,0,42,4,1,47,1,1,6.250,6.250,6.250,19.215,1.435,0.482,-12.884,4.646,5.411,5.319(28%),0.094(7%),0.096(20%),13.896(72%),1.341(93%),0.386(80%)
../syn/ret_I016_O016_D001,5870,607,26,0,26,25,3,44,26,1,26,6.250,6.250,6.250,10.249,1.789,9.477,-4.143,4.331,-3.432,3.004(30%),0.095(6%),3.077(33%),7.245(70%),1.694(94%),6.400(67%)
../syn/ret_I016_O016_D002,5674,1303,26,0,23,16,3,51,26,1,23,6.250,6.250,6.250,10.063,0.750,9.513,-3.882,5.431,-3.331,2.696(27%),0.098(14%),2.916(31%),7.367(73%),0.652(86%),6.597(69%)
../syn/ret_I016_O016_D003,5711,1203,24,0,0,19,3,1,24,1,1,6.250,6.250,6.250,9.548,1.100,0.781,-3.169,5.008,5.187,2.872(31%),0.096(9%),0.095(13%),6.676(69%),1.004(91%),0.686(87%)
../syn/ret_I016_O016_D004,5908,987,26,0,21,53,3,47,26,1,22,6.250,6.250,6.250,10.765,1.947,9.340,-4.665,4.203,-3.237,3.211(30%),0.096(5%),2.778(30%),7.554(70%),1.851(95%),6.562(70%)
../syn/ret_I016_O016_D005,5825,906,25,19,3,44,43,16,25,19,4,6.250,6.250,6.250,9.813,8.581,3.649,-3.621,-2.386,2.442,2.776(29%),2.645(31%),0.539(15%),7.037(71%),5.936(69%),3.110(85%)
../syn/ret_I032_O016_D000,19907,0,74,0,0,59,4,1,74,1,1,6.250,6.250,6.250,32.070,1.103,0.367,-25.754,5.015,5.581,8.678(28%),0.094(9%),0.096(27%),23.392(72%),1.009(91%),0.271(73%)
../syn/ret_I032_O016_D001,19411,2119,37,30,0,58,51,1,37,30,1,6.250,6.250,6.250,19.520,16.408,0.562,-13.434,-10.276,5.598,4.503(24%),2.837(18%),0.093(17%),15.017(76%),13.571(82%),0.469(83%)
../syn/ret_I032_O016_D002,19712,3088,36,0,28,49,4,51,37,1,28,6.250,6.250,6.250,19.063,0.749,16.437,-12.653,5.374,-10.606,4.046(22%),0.099(14%),3.617(23%),15.017(78%),0.650(86%),12.820(77%)
../syn/ret_I032_O016_D003,19942,3039,35,0,36,62,4,56,35,1,36,6.250,6.250,6.250,18.081,1.880,17.145,-12.055,4.234,-11.024,3.835(22%),0.098(6%),3.959(24%),14.246(78%),1.782(94%),13.186(76%)
../syn/ret_I032_O016_D004,19842,2812,33,0,35,59,4,58,33,1,35,6.250,6.250,6.250,16.655,1.384,15.876,-10.540,4.737,-9.709,3.810(23%),0.097(8%),3.925(25%),12.845(77%),1.287(92%),11.951(75%)
../syn/ret_I032_O016_D005,20443,3007,37,0,38,53,2,52,37,1,39,6.250,6.250,6.250,19.390,2.155,16.860,-13.072,3.962,-11.033,4.523(24%),0.097(5%),4.578(28%),14.867(76%),2.058(95%),12.282(72%)
../syn/ret_I032_O016_D006,19874,2521,33,0,2,59,4,1,33,1,3,6.250,6.250,6.250,16.866,1.124,1.833,-10.752,5.021,4.309,3.772(23%),0.096(9%),0.361(20%),13.094(77%),1.028(91%),1.472(80%)
../syn/ret_I032_O016_D007,20167,2685,34,0,1,46,3,1,34,1,2,6.250,6.250,6.250,17.016,0.549,1.997,-10.796,5.582,3.947,4.377(26%),0.096(18%),0.269(14%),12.639(74%),0.453(82%),1.728(86%)
../syn/retfan_I016_O016_D000,6397,0,49,0,0,38,1,1,49,1,1,6.250,6.250,6.250,19.334,0.667,0.426,-13.055,5.452,5.449,5.183(27%),0.094(15%),0.096(23%),14.151(73%),0.573(85%),0.330(77%)
../syn/retfan_I016_O016_D001,6280,674,26,0,25,26,1,16,26,1,25,6.250,6.250,6.250,10.026,0.963,9.732,-3.894,5.256,-3.566,3.216(33%),0.096(10%),3.032(32%),6.810(67%),0.867(90%),6.700(68%)
../syn/retfan_I016_O016_D002,6414,1394,24,0,21,26,1,15,24,1,21,6.250,6.250,6.250,9.483,0.832,8.885,-3.341,5.333,-2.802,2.804(30%),0.093(12%),2.617(30%),6.679(70%),0.739(88%),6.268(70%)
../syn/retfan_I016_O016_D003,6304,1351,24,0,21,30,1,15,24,1,21,6.250,6.250,6.250,9.498,0.695,9.270,-3.502,5.439,-3.101,2.970(32%),0.098(15%),2.415(27%),6.528(68%),0.597(85%),6.855(73%)
../syn/retfan_I016_O016_D004,6435,980,26,0,21,31,1,16,26,1,22,6.250,6.250,6.250,10.812,0.586,9.225,-4.306,5.542,-3.519,3.288(31%),0.099(17%),2.215(25%),7.524(69%),0.487(83%),7.010(75%)
../syn/retfan_I016_O016_D005,6390,997,26,0,21,28,1,16,26,1,21,6.250,6.250,6.250,11.173,0.517,9.044,-4.632,5.657,-3.393,2.895(26%),0.094(19%),2.279(26%),8.278(74%),0.423(81%),6.765(74%)
../syn/retfan_I032_O016_D000,23429,0,82,0,0,56,1,1,82,1,1,6.250,6.250,6.250,37.536,0.608,0.606,-30.971,5.542,5.102,10.089(27%),0.098(17%),0.095(16%),27.447(73%),0.510(83%),0.511(84%)
../syn/retfan_I032_O016_D001,21976,2357,38,0,37,41,1,16,38,1,37,6.250,6.250,6.250,19.833,0.876,18.519,-13.640,5.152,-12.506,4.576(24%),0.094(11%),4.171(23%),15.257(76%),0.782(89%),14.348(77%)
../syn/retfan_I032_O016_D002,21517,3590,34,36,1,16,41,1,34,37,1,6.250,6.250,6.250,17.784,16.822,0.588,-11.469,-10.746,5.423,4.134(24%),3.996(24%),0.158(27%),13.650(76%),12.826(76%),0.430(73%)
../syn/retfan_I032_O016_D003,21714,3158,34,0,22,51,1,15,34,1,22,6.250,6.250,6.250,21.039,1.612,12.067,-14.524,4.517,-6.285,3.655(18%),0.096(6%),2.382(20%),17.384(82%),1.516(94%),9.685(80%)
../syn/retfan_I032_O016_D004,22240,2935,32,0,38,41,1,70,33,1,39,6.250,6.250,6.250,20.670,0.455,18.734,-14.246,5.743,-13.163,4.069(20%),0.098(22%),4.465(24%),16.601(80%),0.357(78%),14.269(76%)
../syn/retfan_I032_O016_D005,23289,3471,41,0,26,42,1,14,41,1,27,6.250,6.250,6.250,19.387,0.576,12.386,-12.976,5.563,-6.868,4.598(24%),0.096(17%),2.846(23%),14.789(76%),0.480(83%),9.540(77%)
../syn/retfan_I032_O016_D006,21901,2992,37,0,31,40,1,15,37,1,31,6.250,6.250,6.250,17.393,0.793,15.517,-11.192,5.405,-9.499,4.243(25%),0.099(13%),3.841(25%),13.150(75%),0.694(87%),11.676(75%)
../syn/retfan_I032_O016_D007,22362,3207,39,0,1,39,1,1,39,1,2,6.250,6.250,6.250,19.102,0.954,2.243,-12.620,5.109,3.426,5.064(27%),0.099(11%),0.244(11%),14.038(73%),0.855(89%),1.999(89%)
src/rtl/mux/mux.vhd 0 → 100644
+ 60
− 0
View file @ 2d47bd6d
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mux is
generic(
AW : natural := 12;
DW : natural := 32;
delay : natural := 3 -- delay in clock cycles for pipeline register
);
port(
clk : in std_logic;
sel : out std_logic_vector(AW - 1 downto 0);
input : in std_logic_vector(DW * (2**AW) - 1 downto 0);
sink_valid : in std_logic;
source_valid : out std_logic;
output : out std_logic_vector(DW - 1 downto 0)
);
end entity mux;
architecture RTL of mux is
signal sel_int : integer range 0 to 2**AW - 1;
signal output_comb : std_logic_vector(DW - 1 downto 0);
-- pipeline
type sr_t is array (integer range <>) of std_logic_vector(DW - 1 downto 0);
signal sr : sr_t(0 to delay);
signal sr_v : std_logic_vector(0 to delay);
attribute shreg_extract : string;
attribute shreg_extract of sr : signal is "no";
attribute shreg_extract of sr_v : signal is "no";
attribute syn_srlstyle : string;
attribute syn_srlstyle of sr : signal is "registers";
attribute syn_srlstyle of sr_v : signal is "registers";
begin
sel_int <= to_integer(unsigned(sel));
output_comb <= input((sel_int + 1) * DW - 1 downto sel_int * DW);
sr_p : process(all) is
begin
sr(0) <= output_comb;
sr_v(0) <= sink_valid;
if rising_edge(clk) then
for i in 1 to delay loop
sr(i) <= sr(i - 1);
sr_v(i) <= sr_v(i - 1);
end loop;
end if;
end process sr_p;
output <= sr(delay);
source_valid <= sr_v(delay);
end architecture RTL;
src/rtl/mux/wrapper_mux.vhd 0 → 100644
+ 156
− 0
View file @ 2d47bd6d
----------------------------------------------------------------------------------------------------------------------
-- Title : wrapper
-- Project : MUCTPI
----------------------------------------------------------------------------------------------------------------------
-- File : wrapper.vhd
-- Author : Marcos Oliveira
-- Company : CERN
-- Created : 2018-12-05
-- Last update: 2019-02-05
-- Platform : Vivado 2017.2 and Mentor Modelsim SE-64 10.4a
-- Standard : VHDL'93/02
----------------------------------------------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2018 CERN
----------------------------------------------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-12-05 1.0 msilvaol Created
----------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.math_real.all;
entity wrapper_mux is
generic(
AW : natural := 12;
DW : natural := 32;
delay : natural := 3 -- delay in clock cycles for pipeline register
);
port(
clk_wrapper : in std_logic;
clk : in std_logic;
input : in std_logic;
output : out std_logic);
attribute syn_loc : string;
attribute syn_pad_type : string;
attribute syn_loc of clk_wrapper :signal is"AU33";
attribute syn_loc of clk :signal is"AV33";
attribute syn_loc of input :signal is"AN32";
attribute syn_loc of output :signal is"AU31";
attribute syn_pad_type of clk_wrapper : signal is "LVCMOS18";
attribute syn_pad_type of clk : signal is "LVCMOS18";
attribute syn_pad_type of input : signal is "LVCMOS18";
attribute syn_pad_type of output : signal is "LVCMOS18";
end entity wrapper_mux;
architecture rtl of wrapper_mux is
--constants
constant i_width : integer := DW*(2**AW)+AW+1;
constant o_width_desired : integer := DW+1;
constant log4_o_width : integer := integer(ceil(log(real(o_width_desired), real(4))));
constant o_width : integer := 4**log4_o_width;
--components
component lfsr is
generic (
WIDTH : natural);
port (
clock : in std_logic;
input_bit : in std_logic;
output_vector : out std_logic_vector(WIDTH-1 downto 0));
end component lfsr;
component reducer is
generic (
input_width_log4 : natural);
port (
clock : in std_logic;
input_vector : in std_logic_vector(4**input_width_log4-1 downto 0);
output_bit : out std_logic);
end component reducer;
signal input_vector : std_logic_vector(i_width-1 downto 0) := (others => '0');
signal input_slr : std_logic_vector(i_width-1 downto 0) := (others => '0');
signal output_vector : std_logic_vector(o_width-1 downto 0) := (others => '0');
signal output_slr : std_logic_vector(o_width-1 downto 0) := (others => '0');
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of lsfr_1 : label is "TRUE";
attribute DONT_TOUCH of reducer_1 : label is "TRUE";
begin -- architecture rtl
lsfr_1 : lfsr
generic map (
WIDTH => i_width)
port map (
clock => clk_wrapper,
input_bit => input,
output_vector => input_vector);
shift_reg_tap_i : entity work.shift_reg_tap
generic map (
dw => i_width,
tw => 4)
port map (
clk => clk,
ce => '1',
tap => (others => '1'),
input => input_vector,
output => input_slr);
shift_reg_tap_o : entity work.shift_reg_tap
generic map (
dw => o_width,
tw => 4)
port map (
clk => clk,
ce => '1',
tap => (others => '1'),
input => output_vector,
output => output_slr);
reducer_1 : reducer
generic map (
input_width_log4 => log4_o_width)
port map (
clock => clk_wrapper,
input_vector => output_slr,
output_bit => output);
----------------------------------------------------------------------------------------------------------------------
-- Logic being tested
----------------------------------------------------------------------------------------------------------------------
mux_1 : entity work.mux
generic map(
AW => AW,
DW => DW,
delay => delay
)
port map(
clk => clk,
sel => input_slr(DW * (2**AW) + AW downto DW * (2**AW) +1),
input => input_slr(DW * (2**AW) downto 1),
sink_valid => input_slr(0),
source_valid => output_vector(0),
output => output_vector(DW downto 1)
);
end architecture rtl;
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