Commit adf7fd45 authored by Stewart Martin-Haugh's avatar Stewart Martin-Haugh Committed by Vakhtang Tsulaia
Browse files

Only retrieve tools in initialize() methods ATR-24078

parent d72ff265
......@@ -45,6 +45,8 @@ namespace LVL1 {
virtual void execute() override ;
virtual StatusCode initialize() override ;
virtual StatusCode executegFEXSim(gTowersIDs tmp) override;
virtual std::vector<uint32_t> getgRhoTOBs() const override;
......
......@@ -120,13 +120,11 @@ StatusCode eFEXDriver::finalize()
std::unique_ptr<eTowerContainer> local_eTowerContainerRaw = std::make_unique<eTowerContainer>();
// STEP 1 - Make some eTowers and fill the local container
ATH_CHECK( m_eTowerBuilderTool.retrieve() );
m_eTowerBuilderTool->init(local_eTowerContainerRaw);
local_eTowerContainerRaw->clearContainerMap();
local_eTowerContainerRaw->fillContainerMap();
// STEP 2 - Do the supercell-tower mapping - put this information into the eTowerContainer
ATH_CHECK( m_eSuperCellTowerMapperTool.retrieve() );
ATH_CHECK(m_eSuperCellTowerMapperTool->AssignSuperCellsToTowers(local_eTowerContainerRaw));
ATH_CHECK(m_eSuperCellTowerMapperTool->AssignTriggerTowerMapper(local_eTowerContainerRaw));
......@@ -168,7 +166,6 @@ StatusCode eFEXDriver::finalize()
ATH_CHECK(eTowerContainerSG.record(std::move(/*my_eTowerContainerRaw*/local_eTowerContainerRaw)));
// STEP 4 - Set up the eFEXSysSim
ATH_CHECK( m_eFEXSysSimTool.retrieve() );
m_eFEXSysSimTool->init();
// STEP 5 - Do some monitoring
......
......@@ -56,6 +56,10 @@ StatusCode eFEXFPGA::initialize()
{
ATH_CHECK(m_eFEXFPGA_eTowerContainerKey.initialize());
ATH_CHECK( m_eFEXegAlgoTool.retrieve() );
ATH_CHECK( m_eFEXtauAlgoTool.retrieve() );
ATH_CHECK(m_l1MenuKey.initialize());
return StatusCode::SUCCESS;
......@@ -105,8 +109,6 @@ StatusCode eFEXFPGA::execute(eFEXOutputCollection* inputOutputCollection){
{m_eTowersIDs[iphi+1][ieta-1], m_eTowersIDs[iphi+1][ieta], m_eTowersIDs[iphi+1][ieta+1]},
};
ATH_CHECK( m_eFEXegAlgoTool.retrieve() );
ATH_CHECK( m_eFEXegAlgoTool->safetyTest() );
m_eFEXegAlgoTool->setup(tobtable);
......@@ -222,8 +224,6 @@ StatusCode eFEXFPGA::execute(eFEXOutputCollection* inputOutputCollection){
{m_eTowersIDs[iphi+1][ieta-1], m_eTowersIDs[iphi+1][ieta], m_eTowersIDs[iphi+1][ieta+1]},
};
ATH_CHECK( m_eFEXtauAlgoTool.retrieve() );
ATH_CHECK( m_eFEXtauAlgoTool->safetyTest() );
m_eFEXtauAlgoTool->setup(tobtable);
......
......@@ -33,6 +33,7 @@ namespace LVL1 {
StatusCode eFEXSim::initialize()
{
ATH_CHECK( m_eFEXFPGATool.retrieve() );
return StatusCode::SUCCESS;
}
......@@ -82,7 +83,6 @@ StatusCode eFEXSim::NewExecute(int tmp_eTowersIDs_subset[10][18], eFEXOutputColl
int tmp_eTowersIDs_subset_FPGA[10][6];
ATH_CHECK( m_eFEXFPGATool.retrieve() );
//FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
memset(tmp_eTowersIDs_subset_FPGA, 0, sizeof tmp_eTowersIDs_subset_FPGA);
......
......@@ -64,6 +64,8 @@ namespace LVL1 {
ATH_CHECK( m_eFEXFPGATowerIdProviderTool.retrieve() );
ATH_CHECK( m_eFEXFPGATool.retrieve() );
return StatusCode::SUCCESS;
}
......@@ -107,7 +109,6 @@ namespace LVL1 {
// do mapping with preloaded csv file if it is available
if (m_eFEXFPGATowerIdProviderTool->ifhaveinputfile()) {
ATH_CHECK( m_eFEXFPGATool.retrieve() );
int tmp_eTowersIDs_subset_eFEX[10][18];
for (int i_efex{ 0 }; i_efex < 24; i_efex++) {
ATH_CHECK(m_eFEXFPGATowerIdProviderTool->getRankedTowerIDineFEX(i_efex, tmp_eTowersIDs_subset_eFEX));
......
......@@ -89,13 +89,11 @@ StatusCode gFEXDriver::initialize()
// ATH_CHECK(gFEXOutputCollectionSG.record(std::move(my_gFEXOutputCollection)));
// STEP 2 - Make some gTowers and fill the local container
ATH_CHECK( m_gTowerBuilderTool.retrieve() );
m_gTowerBuilderTool->init(local_gTowerContainerRaw);
local_gTowerContainerRaw->clearContainerMap();
local_gTowerContainerRaw->fillContainerMap();
// STEP 3 - Do the supercell-tower mapping - put this information into the gTowerContainer
ATH_CHECK( m_gSuperCellTowerMapperTool.retrieve() );
ATH_CHECK(m_gSuperCellTowerMapperTool->AssignSuperCellsToTowers(local_gTowerContainerRaw));
ATH_CHECK(m_gSuperCellTowerMapperTool->AssignTriggerTowerMapper(local_gTowerContainerRaw));
......@@ -104,7 +102,6 @@ StatusCode gFEXDriver::initialize()
ATH_CHECK(gTowerContainerSG.record(std::move(local_gTowerContainerRaw)));
// STEP 5 - Set up the gFEXSysSim
ATH_CHECK( m_gFEXSysSimTool.retrieve() );
// STEP 6 - Run the gFEXSysSim
ATH_CHECK(m_gFEXSysSimTool->execute());
......
......@@ -45,6 +45,12 @@ namespace LVL1 {
gFEXSim::~gFEXSim(){
}
StatusCode gFEXSim::initialize(){
ATH_CHECK( m_gFEXFPGA_Tool.retrieve() );
ATH_CHECK( m_gFEXJetAlgoTool.retrieve() );
return StatusCode::SUCCESS;
}
void gFEXSim::execute(){
}
......@@ -65,7 +71,6 @@ StatusCode gFEXSim::executegFEXSim(gTowersIDs tmp_gTowersIDs_subset){
gTowersForward CNtwr = {{{0}}};
ATH_CHECK( m_gFEXFPGA_Tool.retrieve() );
//FPGA A----------------------------------------------------------------------------------------------------------------------------------------------
gTowersCentral tmp_gTowersIDs_subset_centralFPGA;
......@@ -155,7 +160,6 @@ StatusCode gFEXSim::executegFEXSim(gTowersIDs tmp_gTowersIDs_subset){
std::array<uint32_t, 7> BTOB2_dat = {0};
// Retrieve the gFEXJetAlgoTool
ATH_CHECK( m_gFEXJetAlgoTool.retrieve() );
// Pass the energy matrices to the algo tool, and run the algorithms
auto tobs_v = m_gFEXJetAlgoTool->largeRfinder(Atwr, Btwr, CNtwr, CPtwr,
......
......@@ -312,4 +312,4 @@ namespace LVL1 {
}
} // end of namespace bracket
\ No newline at end of file
} // end of namespace bracket
......@@ -135,13 +135,11 @@ StatusCode jFEXDriver::finalize()
// STEP 2 - Make some jTowers and fill the local container
ATH_CHECK( m_jTowerBuilderTool.retrieve() );
m_jTowerBuilderTool->init(local_jTowerContainerRaw);
local_jTowerContainerRaw->clearContainerMap();
local_jTowerContainerRaw->fillContainerMap();
// STEP 3 - Do the supercell-tower mapping - put this information into the jTowerContainer
ATH_CHECK( m_jSuperCellTowerMapperTool.retrieve() );
ATH_CHECK(m_jSuperCellTowerMapperTool->AssignSuperCellsToTowers(local_jTowerContainerRaw));
ATH_CHECK(m_jSuperCellTowerMapperTool->AssignTriggerTowerMapper(local_jTowerContainerRaw));
......@@ -153,7 +151,6 @@ StatusCode jFEXDriver::finalize()
ATH_CHECK(jTowerContainerSG.record(std::move(/*my_jTowerContainerRaw*/local_jTowerContainerRaw)));
// STEP 5 - Set up the jFEXSysSim
ATH_CHECK( m_jFEXSysSimTool.retrieve() );
m_jFEXSysSimTool->init();
// STEP 6 - Run THE jFEXSysSim
......
......@@ -66,6 +66,7 @@ StatusCode jFEXFPGA::initialize()
ATH_CHECK(m_jFEXFPGA_jTowerContainerKey.initialize());
ATH_CHECK(m_jFEXFPGA_jFEXOutputCollectionKey.initialize());
ATH_CHECK(m_l1MenuKey.initialize());
ATH_CHECK( m_jFEXtauAlgoTool.retrieve());
return StatusCode::SUCCESS;
}
......@@ -298,7 +299,6 @@ StatusCode jFEXFPGA::execute() {
//FCAL region algorithm
if(m_jfexid ==0 || m_jfexid ==5) {
ATH_CHECK(m_jFEXForwardJetsAlgoTool->initialize());
ATH_CHECK(m_jFEXForwardJetsAlgoTool->safetyTest());
m_jFEXForwardJetsAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
m_jFEXForwardJetsAlgoTool->setup(m_jTowersIDs_Wide,m_jfexid,m_id);
......@@ -442,7 +442,6 @@ StatusCode jFEXFPGA::execute() {
}
}
ATH_CHECK( m_jFEXtauAlgoTool.retrieve());
ATH_CHECK( m_jFEXtauAlgoTool->safetyTest());
m_jFEXtauAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
m_jFEXtauAlgoTool->setup(TT_searchWindow_ID,TT_seed_ID);
......
......@@ -34,6 +34,7 @@ namespace LVL1 {
StatusCode jFEXSim::initialize()
{
ATH_CHECK( m_jFEXFPGATool.retrieve() );
return StatusCode::SUCCESS;
}
......@@ -116,8 +117,6 @@ namespace LVL1 {
// 2.4 -> 5.6 [core is 3.2 to 4.8] // FPGA 2
// 4.0 -> 0.8 [core is 4.8 to 6.4] // FPGA 3
ATH_CHECK( m_jFEXFPGATool.retrieve() );
//FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
// 5.6 -> 2.4 [core is 0.0 to 1.6]
......@@ -361,8 +360,6 @@ namespace LVL1 {
// 2.4 -> 5.6 [core is 3.2 to 4.8] // FPGA 2
// 4.0 -> 0.8 [core is 4.8 to 6.4] // FPGA 3
ATH_CHECK( m_jFEXFPGATool.retrieve() );
//FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
// 5.6 -> 2.4 [core is 0.0 to 1.6]
......@@ -595,7 +592,6 @@ StatusCode jFEXSim::ExecuteBarrel(int tmp_jTowersIDs_subset[FEXAlgoSpaceDefs::jF
int tmp_jTowersIDs_subset_FPGA[nrows][ncols];
ATH_CHECK( m_jFEXFPGATool.retrieve() );
//FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
......
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