Skip to content
Snippets Groups Projects
Commit 41a0b703 authored by David Gabriel Monk's avatar David Gabriel Monk
Browse files

Merge branch 'heterogeneous-dtc' into 'configurable-thresholds' 

# Conflicts:
#   common/firmware/cfg/module.dep
parents 00da54eb 4dd40b0f
No related branches found
No related tags found
2 merge requests!405 bits thresholds registers,!35Added configurable threshold for each input link
Pipeline #6150985 passed
Stage: Static Analysis
Stage: Make Project
Stage: Pre-build Checks
Stage: Synthesis
Stage: Implementation
Stage: Package
Stage: Upload to Registry
Hide whitespace changes
Inline Side-by-side
Showing
with 262 additions and 112 deletions
common/addr_table/mprocessor.xml
+ 8
− 3
View file @ 41a0b703
...@@ -10,9 +10,14 @@ ...@@ -10,9 +10,14 @@
<node id="header_user_bits" address="0x1"/> <node id="header_user_bits" address="0x1"/>
</node> </node>
<node id="csr" address="0x24" description="MProcessor control and status" fwinfo="endpoint;width=2"> <node id="csr" address="0x30" description="MProcessor control and status" fwinfo="endpoint;width=3">
<node id="header_start_select" address="0x0" mask="0x7"/> <node id="header_start_select" address="0x0" mask="0x7"/>
<node id="lff" address="0x2" mask="0x0001"/> <node id="occupancy_windowL" address="0x1"/>
<node id="super_id" address="0x3"/> <node id="occupancy_windowH" address="0x2" mask="0x000f"/>
<node id="lff" address="0x4" mask="0x0001"/>
<node id="super_id" address="0x5"/>
<node id="occupancy_max_value" address="0x6"/>
</node> </node>
<node id="occupancy_mem" address="0x400" size="0x100" mode="incremental" fwinfo="endpoint;width=8"/>
</node> </node>
common/firmware/cfg/module.dep
+ 1
− 0
View file @ 41a0b703
...@@ -11,6 +11,7 @@ src LinkCombinerCore.vhd ...@@ -11,6 +11,7 @@ src LinkCombinerCore.vhd
src LinkCombinerIPBus.vhd src LinkCombinerIPBus.vhd
src --vhdl2008 TrackReconstructor.vhd src --vhdl2008 TrackReconstructor.vhd
src mprocessor_data_types.vhd src mprocessor_data_types.vhd
src PayloadHeaderGenerator.vhd
src ipbus_decode_link_aggregator.vhd src ipbus_decode_link_aggregator.vhd
src ipbus_decode_mprocessor.vhd src ipbus_decode_mprocessor.vhd
......
common/firmware/hdl/LinkAggregatorCore.vhd
+ 3
− 2
View file @ 41a0b703
...@@ -11,7 +11,8 @@ use work.mprocessor_data_types.all; ...@@ -11,7 +11,8 @@ use work.mprocessor_data_types.all;
entity LinkAggregatorCore is entity LinkAggregatorCore is
generic ( generic (
N_LINKS : integer N_LINKS : integer;
INDEX : integer := 0
); );
port ( port (
--- Input Ports --- --- Input Ports ---
...@@ -171,7 +172,7 @@ begin ...@@ -171,7 +172,7 @@ begin
if rising_edge(clk_p) then if rising_edge(clk_p) then
wr_en_array_cache <= (others => '0'); wr_en_array_cache <= (others => '0');
wr_en_array_cache(to_integer(unsigned(links_in(i).data(21 downto 19)))) <= links_in(i).valid; wr_en_array_cache(to_integer(unsigned(links_in(i).data(21 downto 19)))) <= links_in(i).valid;
data_in <= std_logic_vector(to_unsigned(i, 4)) & links_in(i).data(cFIFOWidth - 1 - 4 downto 0); data_in <= std_logic_vector(to_unsigned(INDEX*N_LINKS + i, 4)) & links_in(i).data(cFIFOWidth - 1 - 4 downto 0);
end if; end if;
end process pRouteInputData; end process pRouteInputData;
......
common/firmware/hdl/LinkAggregatorIPBus.vhd
+ 4
− 2
View file @ 41a0b703
...@@ -12,7 +12,8 @@ use work.ipbus_decode_link_aggregator.all; ...@@ -12,7 +12,8 @@ use work.ipbus_decode_link_aggregator.all;
entity LinkAggregatorIPBus is entity LinkAggregatorIPBus is
generic ( generic (
N_LINKS : integer N_LINKS : integer;
INDEX : integer := 0
); );
port ( port (
--- Input Ports --- --- Input Ports ---
...@@ -201,7 +202,8 @@ begin ...@@ -201,7 +202,8 @@ begin
LinkAggregatorInstance: entity work.LinkAggregatorCore LinkAggregatorInstance: entity work.LinkAggregatorCore
--==============================-- --==============================--
generic map ( generic map (
N_LINKS => N_LINKS N_LINKS => N_LINKS,
INDEX => INDEX
) )
port map ( port map (
--- Input Ports --- --- Input Ports ---
......
common/firmware/hdl/LinkCombinerCore.vhd
+ 22
− 70
View file @ 41a0b703
...@@ -5,6 +5,7 @@ use work.emp_data_types.all; ...@@ -5,6 +5,7 @@ use work.emp_data_types.all;
use work.dtc_link_maps.all; use work.dtc_link_maps.all;
use work.dtc_constants.all; use work.dtc_constants.all;
use work.dtc_data_types.all; use work.dtc_data_types.all;
use IEEE.std_logic_misc.all;
entity LinkCombinerCore is entity LinkCombinerCore is
...@@ -19,14 +20,14 @@ entity LinkCombinerCore is ...@@ -19,14 +20,14 @@ entity LinkCombinerCore is
output_enable : in std_logic := '0'; output_enable : in std_logic := '0';
links_in : in ldata(N_INPUT_LINKS - 1 downto 0); links_in : in ldata(N_INPUT_LINKS - 1 downto 0);
packet_start : in std_logic; packet_start : in std_logic;
header_in : in tCICHeaderArray(cNumberOfFEModules * cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0'))); payload_header : in std_logic_vector(127 downto 0) := (others => '0');
header_user_bits : in std_logic_vector(31 downto 0) := (others => '0');
--- Ouput Ports --- --- Ouput Ports ---
link_out : out lword := LWORD_NULL; link_out : out lword := LWORD_NULL;
--- Debug Ports --- --- Debug Ports ---
debug : out lword := LWORD_NULL; debug : out lword := LWORD_NULL;
debug_super_id : out std_logic_vector(31 downto 0); debug_super_id : out std_logic_vector(31 downto 0);
debug_fifo : out std_logic_vector(31 downto 0) := (others => '0') debug_fifo : out std_logic_vector(31 downto 0) := (others => '0');
debug_packet_size : out lword := LWORD_NULL
); );
end LinkCombinerCore; end LinkCombinerCore;
...@@ -87,7 +88,7 @@ architecture Behavioral of LinkCombinerCore is ...@@ -87,7 +88,7 @@ architecture Behavioral of LinkCombinerCore is
constant cNullValidArray : std_logic_vector(N_INPUT_LINKS - 1 downto 0) := (others => '0'); constant cNullValidArray : std_logic_vector(N_INPUT_LINKS - 1 downto 0) := (others => '0');
constant cFullEmptyArray : std_logic_vector(N_INPUT_LINKS - 1 downto 0) := (others => '1'); constant cFullEmptyArray : std_logic_vector(N_INPUT_LINKS - 1 downto 0) := (others => '1');
-- Signals -- Signals
signal input_dout_array : tWordArray(0 to N_INPUT_LINKS - 1) := (others => (others => '0')); signal input_dout_array : tWordArray(0 to N_INPUT_LINKS - 1) := (others => (others => '0'));
signal input_rd_en_array : std_logic_vector(N_INPUT_LINKS - 1 downto 0) := (others => '0'); signal input_rd_en_array : std_logic_vector(N_INPUT_LINKS - 1 downto 0) := (others => '0');
signal input_almost_empty_array, input_valid_array : std_logic_vector(N_INPUT_LINKS - 1 downto 0) := (others => '0'); signal input_almost_empty_array, input_valid_array : std_logic_vector(N_INPUT_LINKS - 1 downto 0) := (others => '0');
...@@ -113,7 +114,6 @@ architecture Behavioral of LinkCombinerCore is ...@@ -113,7 +114,6 @@ architecture Behavioral of LinkCombinerCore is
signal output_rd_en : std_logic := '0'; signal output_rd_en : std_logic := '0';
signal counter : integer := 0; signal counter : integer := 0;
signal status_sr : tStatusShiftRegister := (others => (others => '0'));
signal bcid_sr : tBCIDShiftRegister := (others => (others => '0')); signal bcid_sr : tBCIDShiftRegister := (others => (others => '0'));
signal super_id : unsigned(32 - 1 downto 0) := (others => '0'); signal super_id : unsigned(32 - 1 downto 0) := (others => '0');
...@@ -124,6 +124,7 @@ architecture Behavioral of LinkCombinerCore is ...@@ -124,6 +124,7 @@ architecture Behavioral of LinkCombinerCore is
begin begin
--==============================-- --==============================--
genInputLinkBuffers : for i in 0 to N_INPUT_LINKS - 1 generate genInputLinkBuffers : for i in 0 to N_INPUT_LINKS - 1 generate
--==============================-- --==============================--
...@@ -193,6 +194,8 @@ begin ...@@ -193,6 +194,8 @@ begin
variable data_count : unsigned(7 downto 0); variable data_count : unsigned(7 downto 0);
begin begin
if rising_edge(clk_p) then if rising_edge(clk_p) then
debug_packet_size <= LWORD_NULL;
output_valid_previous <= output_valid; output_valid_previous <= output_valid;
if output_valid = '1' and output_rd_en_check = '1' then if output_valid = '1' and output_rd_en_check = '1' then
link_out.valid <= '1'; link_out.valid <= '1';
...@@ -212,6 +215,9 @@ begin ...@@ -212,6 +215,9 @@ begin
if data_count >= 2 and output_readout_countdown = 0 then if data_count >= 2 and output_readout_countdown = 0 then
output_rd_en_check <= output_enable; output_rd_en_check <= output_enable;
output_readout_countdown <= to_integer(data_count); output_readout_countdown <= to_integer(data_count);
debug_packet_size.valid <= '1';
debug_packet_size.data(7 downto 0) <= output_data_count;
elsif output_almost_full = '1' and output_readout_countdown = 0 then elsif output_almost_full = '1' and output_readout_countdown = 0 then
output_rd_en_check <= output_enable; output_rd_en_check <= output_enable;
output_readout_countdown <= to_integer(data_count); output_readout_countdown <= to_integer(data_count);
...@@ -266,7 +272,7 @@ begin ...@@ -266,7 +272,7 @@ begin
begin begin
if rising_edge(clk_p) then if rising_edge(clk_p) then
-- Iterate pointer to successively empty the input FIFOs -- Iterate pointer to successively empty the input FIFOs
if input_data_valid = '1' and counter = 4 then if input_data_valid = '1' and counter = 3 then
if input_almost_empty_array(output_pointer) = '0' then if input_almost_empty_array(output_pointer) = '0' then
input_rd_en_array(output_pointer) <= '1'; input_rd_en_array(output_pointer) <= '1';
else else
...@@ -284,6 +290,8 @@ begin ...@@ -284,6 +290,8 @@ begin
end if; end if;
end if; end if;
else else
output_pointer <= 0;
next_pointer_location := 0;
input_rd_en_array(output_pointer) <= '0'; input_rd_en_array(output_pointer) <= '0';
end if; end if;
...@@ -291,7 +299,7 @@ begin ...@@ -291,7 +299,7 @@ begin
if packet_start = '1' then if packet_start = '1' then
counter <= 0; counter <= 0;
else else
if counter < 4 then if counter < 3 then
counter <= counter + 1; counter <= counter + 1;
else else
counter <= counter; counter <= counter;
...@@ -299,83 +307,27 @@ begin ...@@ -299,83 +307,27 @@ begin
end if; end if;
output_pointer_buffered <= output_pointer; output_pointer_buffered <= output_pointer;
output_din <= input_dout_array(output_pointer_buffered); output_din <= input_dout_array(output_pointer_buffered);
output_wr_en <= input_valid_array(output_pointer_buffered); output_wr_en <= input_valid_array(output_pointer_buffered) and (not reset);
if reset = '1' then
packet_stub_count <= (others => '0');
packet_stub_count_previous <= packet_stub_count;
packet_stub_counter_pointer <= 0;
packet_stub_count_done <= '0';
else
if packet_stub_count_done = '0' then
if packet_stub_counter_pointer = (cNumberOfFEModules - 1) * cNumberOfCICs then
packet_stub_count_done <= '1';
end if;
packet_stub_count <= packet_stub_count + unsigned(header_in(packet_stub_counter_pointer).stub_count) + unsigned(header_in(packet_stub_counter_pointer + 1).stub_count);
packet_stub_counter_pointer <= packet_stub_counter_pointer + cNumberOfCICs;
end if;
end if;
if counter = 1 then if counter = 1 then
output_wr_en_buf <= '1';
output_din_buf(63 downto 32) <= header_user_bits;
output_din_buf(31 downto 0) <= std_logic_vector(super_id);
elsif counter = 2 then
output_din_buf <= (others => '0');
output_din_buf(63 downto 56) <= std_logic_vector(packet_stub_count_previous);
output_din_buf(47 downto 36) <= bcid_sr(bcid_sr'high);
output_wr_en_buf <= '1'; output_wr_en_buf <= '1';
if cNumberOfFEModules < 3 then output_din_buf <= payload_header(63 downto 0);
output_din_buf(cNumberOfFEModules * cNumberOfCICs * 9 - 1 downto 0) <= status_sr(status_sr'high); elsif counter = 2 then
else
output_din_buf(2 * cNumberOfCICs * 9 - 1 downto 0) <= status_sr(status_sr'high)(2 * cNumberOfCICs * 9 - 1 downto 0);
end if;
elsif counter = 3 then
output_din_buf <= (others => '0'); output_din_buf <= (others => '0');
output_din_buf(19 downto 0) <= payload_header(83 downto 64);
output_wr_en_buf <= '1'; output_wr_en_buf <= '1';
if cNumberOfFEModules >= 3 and cNumberOfFEModules < 6 then
output_din_buf((cNumberOfFEModules - 2) * cNumberOfCICs * 9 - 1 downto 0) <= status_sr(status_sr'high)(cNumberOfFEModules * cNumberOfCICs * 9 - 1 downto 2 * cNumberOfCICs * 9);
end if;
else else
output_wr_en_buf <= output_wr_en; output_wr_en_buf <= output_wr_en and (not reset);
output_din_buf <= output_din; output_din_buf <= output_din;
end if; end if;
end if; end if;
end process pCombineBuffers; end process pCombineBuffers;
--==============================--
pBufferHeader: process(clk_p)
--==============================--
variable status : std_logic_vector(cNumberOfFEModules * cNumberOfCICs * 9 - 1 downto 0) := (others => '0');
variable bcid : std_logic_vector(12 - 1 downto 0) := (others => '0');
begin
if rising_edge(clk_p) then
if output_reset = '1' then
super_id <= (others => '0');
else
if packet_start = '1' then
for i in cNumberOfFEModules - 1 downto 0 loop
status(i*cNumberOfCICs*9 + 8 downto i*cNumberOfCICs*9) := std_logic_vector(header_in(i*cNumberOfCICs).status);
status(i*cNumberOfCICs*9 + 17 downto i*cNumberOfCICs*9 + 9) := std_logic_vector(header_in(i*cNumberOfCICs + 1).status);
end loop;
status_sr <= status_sr(status_sr'high - 1 downto 0) & status;
bcid := std_logic_vector(header_in(0).bcid);
bcid_sr <= bcid_sr(bcid_sr'high - 1 downto 0) & bcid;
if unsigned(bcid_sr(bcid_sr'high)) > unsigned(bcid_sr(bcid_sr'high - 1)) then
super_id <= super_id + 1;
end if;
end if;
end if;
end if;
end process pBufferHeader;
--==============================-- --==============================--
-- Debug -- Debug
--==============================-- --==============================--
debug.data(31 downto 0) <= std_logic_vector(super_id); debug.data(31 downto 0) <= payload_header(31 downto 0);
debug.data(39 downto 32) <= output_data_count; debug.data(39 downto 32) <= output_data_count;
debug.data(47 downto 40) <= "00" & input_data_count(0); debug.data(47 downto 40) <= "00" & input_data_count(0);
debug.data(51 downto 48) <= std_logic_vector(to_unsigned(counter, 4)); debug.data(51 downto 48) <= std_logic_vector(to_unsigned(counter, 4));
...@@ -385,7 +337,7 @@ begin ...@@ -385,7 +337,7 @@ begin
debug.data(58) <= input_data_valid; debug.data(58) <= input_data_valid;
debug.valid <= '1'; debug.valid <= '1';
debug.strobe <= '1'; debug.strobe <= '1';
debug_super_id <= std_logic_vector(super_id); debug_super_id <= payload_header(31 downto 0);
debug_fifo(7 downto 0) <= output_data_count; debug_fifo(7 downto 0) <= output_data_count;
debug_fifo(8) <= output_full; debug_fifo(8) <= output_full;
debug_fifo(9) <= output_rd_en; debug_fifo(9) <= output_rd_en;
......
common/firmware/hdl/LinkCombinerIPBus.vhd
+ 6
− 6
View file @ 41a0b703
...@@ -21,7 +21,7 @@ entity LinkCombinerIPBus is ...@@ -21,7 +21,7 @@ entity LinkCombinerIPBus is
reset : in std_logic; reset : in std_logic;
links_in : in ldata(N_INPUT_LINKS - 1 downto 0); links_in : in ldata(N_INPUT_LINKS - 1 downto 0);
packet_start : in std_logic; packet_start : in std_logic;
header_in : in tCICHeaderArray(cNumberOfFEModules * cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0'))); payload_header : in std_logic_vector(127 downto 0) := (others => '0');
lff : in std_logic; lff : in std_logic;
output_srst : in std_logic := '0'; output_srst : in std_logic := '0';
--- Ouput Ports --- --- Ouput Ports ---
...@@ -32,7 +32,8 @@ entity LinkCombinerIPBus is ...@@ -32,7 +32,8 @@ entity LinkCombinerIPBus is
ipb_in : in ipb_wbus; ipb_in : in ipb_wbus;
ipb_out : out ipb_rbus; ipb_out : out ipb_rbus;
--- Debug Ports --- --- Debug Ports ---
super_id : out std_logic_vector(31 downto 0) super_id : out std_logic_vector(31 downto 0);
debug_packet_size : out lword := LWORD_NULL
); );
end LinkCombinerIPBus; end LinkCombinerIPBus;
...@@ -108,14 +109,13 @@ begin ...@@ -108,14 +109,13 @@ begin
output_enable => link_combiner_rd_en, output_enable => link_combiner_rd_en,
links_in => masked_input, links_in => masked_input,
packet_start => packet_start, packet_start => packet_start,
header_in => header_in, payload_header => payload_header,
header_user_bits => control_registers(1),
--- Output Ports --- --- Output Ports ---
link_out => link_out, link_out => link_out,
--- Debug Ports --- --- Debug Ports ---
-- debug => link_combiner_debug, -- debug => link_combiner_debug,
debug_super_id => super_id debug_super_id => super_id,
-- debug_fifo => link_aggregator_status_registers(2) debug_packet_size => debug_packet_size
); );
end Behavioral; end Behavioral;
common/firmware/hdl/MProcessor.vhd
+ 66
− 10
View file @ 41a0b703
...@@ -16,14 +16,15 @@ use work.dtc_data_types.all; ...@@ -16,14 +16,15 @@ use work.dtc_data_types.all;
entity MProcessor is entity MProcessor is
generic ( generic (
N_LINKS : integer N_LINKS : integer;
INDEX : integer := 0
); );
port ( port (
--- Input Ports --- --- Input Ports ---
clk_p : in std_logic; clk_p : in std_logic;
links_in : in ldata(N_LINKS - 1 downto 0); links_in : in ldata(N_LINKS - 1 downto 0);
header_in : in tCICHeaderArray(cNumberOfFEModules * cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
header_start_array : in tHeaderStartArray := (others => (others => '0')); header_start_array : in tHeaderStartArray := (others => (others => '0'));
payload_header : in std_logic_vector(127 downto 0) := (others => '0');
gbe_backpressure : in std_logic := '0'; gbe_backpressure : in std_logic := '0';
srst : in std_logic := '0'; srst : in std_logic := '0';
--- Output Ports --- --- Output Ports ---
...@@ -32,7 +33,9 @@ entity MProcessor is ...@@ -32,7 +33,9 @@ entity MProcessor is
ipb_clk : in std_logic; ipb_clk : in std_logic;
ipb_rst : in std_logic; ipb_rst : in std_logic;
ipb_in : in ipb_wbus; ipb_in : in ipb_wbus;
ipb_out : out ipb_rbus ipb_out : out ipb_rbus;
--- Debug Ports ---
debug_readout_reset : out std_logic := '0'
); );
end MProcessor; end MProcessor;
...@@ -47,11 +50,20 @@ architecture Behavorial of MProcessor is ...@@ -47,11 +50,20 @@ architecture Behavorial of MProcessor is
signal aggregated_stubs : ldata(7 downto 0) := (others => LWORD_NULL); signal aggregated_stubs : ldata(7 downto 0) := (others => LWORD_NULL);
signal link_aggregator_input : ldata(N_LINKS - 1 downto 0) := (others => LWORD_NULL); signal link_aggregator_input : ldata(N_LINKS - 1 downto 0) := (others => LWORD_NULL);
signal status_registers : ipb_reg_v(2 - 1 downto 0) := (others => (others => '0')); signal status_registers : ipb_reg_v(3 - 1 downto 0) := (others => (others => '0'));
signal control_registers : ipb_reg_v(1 - 1 downto 0) := (others => (others => '0')); signal control_registers : ipb_reg_v(3 - 1 downto 0) := (others => (others => '0'));
signal super_id : std_logic_vector(31 downto 0) := (others => '0'); signal super_id : std_logic_vector(31 downto 0) := (others => '0');
signal occupancy_trigger_window_lower : std_logic_vector(31 downto 0) := (others => '0');
signal occupancy_trigger_window_upper : std_logic_vector(3 downto 0) := (others => '0');
signal occupancy_trigger_window : std_logic_vector(36 - 1 downto 0) := X"0ffffffff";
signal occupancy_max_value : std_logic_vector(32 - 1 downto 0) := (others => '0');
signal occupancy_histogram_reset : std_logic := '0';
signal debug_packet_size : lword := LWORD_NULL;
begin begin
--==============================-- --==============================--
...@@ -78,8 +90,8 @@ begin ...@@ -78,8 +90,8 @@ begin
MProcessorControlInstance: entity work.ipbus_ctrlreg_v MProcessorControlInstance: entity work.ipbus_ctrlreg_v
--==============================-- --==============================--
generic map( generic map(
N_CTRL => 1, N_CTRL => 3,
N_STAT => 2 N_STAT => 3
) )
port map( port map(
clk => ipb_clk, clk => ipb_clk,
...@@ -94,7 +106,8 @@ begin ...@@ -94,7 +106,8 @@ begin
LinkAggregatorInstance: entity work.LinkAggregatorIPBus LinkAggregatorInstance: entity work.LinkAggregatorIPBus
--==============================-- --==============================--
generic map ( generic map (
N_LINKS => N_LINKS N_LINKS => N_LINKS,
INDEX => INDEX
) )
port map ( port map (
--- Input Ports --- --- Input Ports ---
...@@ -123,7 +136,7 @@ begin ...@@ -123,7 +136,7 @@ begin
reset => readout_reset, reset => readout_reset,
links_in => aggregated_stubs, links_in => aggregated_stubs,
packet_start => packet_start, packet_start => packet_start,
header_in => header_in, payload_header => payload_header,
lff => gbe_backpressure, lff => gbe_backpressure,
output_srst => srst, output_srst => srst,
--- Output Ports --- --- Output Ports ---
...@@ -134,7 +147,8 @@ begin ...@@ -134,7 +147,8 @@ begin
ipb_in => ipb_to_slaves(N_SLV_LINK_COMBINER), ipb_in => ipb_to_slaves(N_SLV_LINK_COMBINER),
ipb_out => ipb_from_slaves(N_SLV_LINK_COMBINER), ipb_out => ipb_from_slaves(N_SLV_LINK_COMBINER),
--- Debug Ports --- --- Debug Ports ---
super_id => super_id super_id => super_id,
debug_packet_size => debug_packet_size
); );
-- --==============================-- -- --==============================--
...@@ -151,5 +165,47 @@ begin ...@@ -151,5 +165,47 @@ begin
status_registers(0)(0) <= gbe_backpressure; status_registers(0)(0) <= gbe_backpressure;
status_registers(1) <= super_id; status_registers(1) <= super_id;
packet_start <= header_start_array(to_integer(unsigned(control_registers(0)(2 downto 0))))(0); packet_start <= header_start_array(to_integer(unsigned(control_registers(0)(2 downto 0))))(0);
debug_readout_reset <= readout_reset;
--==============================--
PacketSizeHistogramInstance : entity work.IPBusHistogram
--==============================--
generic map (
input_width => 8,
bin_width => 32,
data_offset => 0
)
port map (
--- Input Ports ---
clk_p => clk_p,
data_in => debug_packet_size,
histogram_reset => occupancy_histogram_reset,
--- Output Ports ---
max_bin_value => occupancy_max_value,
--- IPBus Ports ---
clk => ipb_clk,
rst => ipb_rst,
ipb_in => ipb_to_slaves(N_SLV_OCCUPANCY_MEM),
ipb_out => ipb_from_slaves(N_SLV_OCCUPANCY_MEM)
);
--==============================--
OccupancyHistogramResetter : entity work.HistogramResetter
--==============================--
port map (
--- Input Ports ---
clk_p => clk_p,
trigger_window => occupancy_trigger_window,
--- Output Ports ---
histogram_reset => occupancy_histogram_reset
);
occupancy_trigger_window_lower <= control_registers(1);
occupancy_trigger_window_upper <= control_registers(2)(3 downto 0);
occupancy_trigger_window <= occupancy_trigger_window_upper & occupancy_trigger_window_lower;
status_registers(2)(32 - 1 downto 0) <= occupancy_max_value;
end Behavorial; end Behavorial;
common/firmware/hdl/PayloadHeaderGenerator.vhd 0 → 100644
+ 109
− 0
View file @ 41a0b703
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.emp_data_types.all;
use work.dtc_link_maps.all;
use work.dtc_constants.all;
use work.dtc_data_types.all;
use IEEE.std_logic_misc.all;
use work.mprocessor_constants.all;
entity PayloadHeaderGenerator is
port (
--- Input Ports ---
clk_p : in std_logic;
reset : in std_logic;
readout_reset : in std_logic;
header_start : in std_logic;
module_header_in : in tCICHeaderArray(cNumberOfFEModules * cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
user_bits : in std_logic_vector(31 downto 0);
--- Ouput Ports ---
header_out : out tPayloadHeaderArray := (others => (others => '0'));
--- Debug Ports ---
debug_super_id : out std_logic_vector(31 downto 0) := (others => '0')
);
end PayloadHeaderGenerator;
architecture Behavioral of PayloadHeaderGenerator is
type tBCIDShiftRegister is array(1 downto 0) of std_logic_vector(12 - 1 downto 0);
type tInputDataCountArray is array(integer range <>) of std_logic_vector(5 downto 0);
signal bcid_sr : tBCIDShiftRegister := (others => (others => '0'));
signal super_id : unsigned(32 - 1 downto 0) := (others => '0');
signal packet_stub_count, packet_stub_count_previous : unsigned(7 downto 0) := (others => '0');
signal packet_stub_counter_pointer : integer := 0;
signal packet_stub_count_done : std_logic := '0';
signal header_word : std_logic_vector(127 downto 0) := (others => '0');
begin
--==============================--
pBufferHeader: process(clk_p)
--==============================--
variable bcid : std_logic_vector(12 - 1 downto 0) := (others => '0');
begin
if rising_edge(clk_p) then
if reset = '1' then
super_id <= (others => '0');
header_word <= (others => '0');
else
if header_start = '1' then
bcid := std_logic_vector(module_header_in(0).bcid);
bcid_sr <= bcid_sr(bcid_sr'high - 1 downto 0) & bcid;
if unsigned(bcid_sr(bcid_sr'high)) > unsigned(bcid_sr(bcid_sr'high - 1)) then
super_id <= super_id + 1;
end if;
end if;
-- header_word <= (others => '0');
header_word(31 downto 0) <= std_logic_vector(super_id);
header_word(63 downto 32) <= user_bits;
header_word(75 downto 64) <= bcid_sr(bcid_sr'high);
end if;
end if;
end process pBufferHeader;
--==============================--
genOutput : for i in 0 to 2 - 1 generate
--==============================--
signal packet_stub_count, packet_stub_count_previous : unsigned(7 downto 0) := (others => '0');
signal packet_stub_counter_pointer : integer := 0;
signal packet_stub_count_done : std_logic := '0';
begin
--==============================--
pCountStubs : process(clk_p)
--==============================--
begin
if rising_edge(clk_p) then
if readout_reset = '1' then
packet_stub_count <= (others => '0');
packet_stub_count_previous <= packet_stub_count;
packet_stub_counter_pointer <= 0;
packet_stub_count_done <= '0';
else
if packet_stub_count_done = '0' then
if packet_stub_counter_pointer = (6 - 1) * cNumberOfCICs then
packet_stub_count_done <= '1';
end if;
packet_stub_count <= packet_stub_count + unsigned(module_header_in((6*i) + packet_stub_counter_pointer).stub_count) + unsigned(module_header_in((6*i) + packet_stub_counter_pointer + 1).stub_count);
packet_stub_counter_pointer <= packet_stub_counter_pointer + cNumberOfCICs;
end if;
end if;
header_out(i)(75 downto 0 ) <= header_word(75 downto 0);
header_out(i)(83 downto 76) <= std_logic_vector(packet_stub_count_previous);
end if;
end process pCountStubs;
end generate ; -- genOutput
debug_super_id <= std_logic_vector(super_id);
end Behavioral;
common/firmware/hdl/mprocessor_constants.vhd
+ 1
− 0
View file @ 41a0b703
...@@ -7,6 +7,7 @@ use work.dtc_link_maps.all; ...@@ -7,6 +7,7 @@ use work.dtc_link_maps.all;
package mprocessor_constants is package mprocessor_constants is
type tHeaderStartArray is array(cNumberOfFEModules - 1 downto 0) of std_logic_vector(1 downto 0); type tHeaderStartArray is array(cNumberOfFEModules - 1 downto 0) of std_logic_vector(1 downto 0);
type tPayloadHeaderArray is array(2 - 1 downto 0) of std_logic_vector(127 downto 0);
function convertSLVtoHeaderStartArray (input_vector : in std_logic_vector(2*cNumberOfFEModules - 1 downto 0)) return tHeaderStartArray; function convertSLVtoHeaderStartArray (input_vector : in std_logic_vector(2*cNumberOfFEModules - 1 downto 0)) return tHeaderStartArray;
......
top/addr_table/emp_payload.xml
+ 10
− 8
View file @ 41a0b703
...@@ -7,17 +7,19 @@ ...@@ -7,17 +7,19 @@
<node id="fe_chan" address="0x200" module="file://dtc_link_interface.xml" fwinfo="endpoint;width=9"/> <node id="fe_chan" address="0x200" module="file://dtc_link_interface.xml" fwinfo="endpoint;width=9"/>
<node id="mprocessor" address="0x400" description="MProcessor control and status" module="file://mprocessor.xml" fwinfo="endpoint;width=7"/>
<node id="mproc_ctrl" address="0x4ff" description="MProcessor channel control" fwinfo="endpoint;width=0">
<node id="chan_sel" mask="0x7f"/>
<node id="srst" mask="0x80"/>
<node id="sync_fastreset" mask="0x100"/>
</node>
<node id="tcds_fast_cmd" address="0x600" module="file://dtc_tcds_fastcmd.xml"/> <node id="tcds_fast_cmd" address="0x600" module="file://dtc_tcds_fastcmd.xml"/>
<node id="link_monitor" address="0x10000" module="file://LinkMonitorInterface.xml"/> <node id="link_monitor" address="0x10000" module="file://LinkMonitorInterface.xml"/>
<node id="mprocessor" address="0x40000" description="MProcessor control and status" module="file://mprocessor.xml" fwinfo="endpoint;width=12"/>
<node id="mproc_ctrl" address="0x4fff0" description="MProcessor channel control" fwinfo="endpoint;width=1">
<node id="control" address="0x0">
<node id="chan_sel" mask="0x7f"/>
<node id="srst" mask="0x80"/>
<node id="sync_fastreset" mask="0x100"/>
</node>
<node id="header_user_bits" address="0x1"/>
</node>
<node id="be_daq" address="0x40000000" module="file://dtc_data_aggregator.xml" fwinfo="endpoint;width=30"/> <node id="be_daq" address="0x40000000" module="file://dtc_data_aggregator.xml" fwinfo="endpoint;width=30"/>
</node> </node>
top/firmware/hdl/emp_payload.vhd
+ 32
− 11
View file @ 41a0b703
...@@ -60,7 +60,8 @@ architecture rtl of emp_payload is ...@@ -60,7 +60,8 @@ architecture rtl of emp_payload is
signal fe_control_registers : ipb_reg_v(0 downto 0); signal fe_control_registers : ipb_reg_v(0 downto 0);
signal fe_status_registers : ipb_reg_v(0 downto 0); signal fe_status_registers : ipb_reg_v(0 downto 0);
signal mproc_channel_sel : ipb_reg_v(0 downto 0); signal mproc_control_registers : ipb_reg_v(1 downto 0);
signal mproc_status_registers : ipb_reg_v(0 downto 0);
signal link_aggr_control : ipb_reg_v(0 downto 0); signal link_aggr_control : ipb_reg_v(0 downto 0);
...@@ -84,6 +85,8 @@ architecture rtl of emp_payload is ...@@ -84,6 +85,8 @@ architecture rtl of emp_payload is
signal orbit_counter : unsigned(31 downto 0) := to_unsigned(0 , 32); signal orbit_counter : unsigned(31 downto 0) := to_unsigned(0 , 32);
signal bunch_counter : unsigned(11 downto 0) := to_unsigned(3564, 12); signal bunch_counter : unsigned(11 downto 0) := to_unsigned(3564, 12);
signal readout_reset : std_logic_vector(cNumberOfMProcessors - 1 downto 0) := (others => '0');
signal payload_headers : tPayloadHeaderArray := (others => (others => '0'));
-- Daqpath -- Daqpath
...@@ -157,18 +160,17 @@ begin ...@@ -157,18 +160,17 @@ begin
); );
--==============================-- --==============================--
mproc_channel_ctrl: entity work.ipbus_reg_v mproc_ctrl: entity work.ipbus_ctrlreg_v
--==============================-- --==============================--
generic map( generic map(
N_REG => 1 N_CTRL => 2
) )
port map( port map(
clk => clk, clk => clk,
reset => rst, reset => rst,
ipbus_in => ipb_to_slaves(N_SLV_MPROC_CTRL), ipbus_in => ipb_to_slaves(N_SLV_MPROC_CTRL),
ipbus_out => ipb_from_slaves(N_SLV_MPROC_CTRL), ipbus_out => ipb_from_slaves(N_SLV_MPROC_CTRL),
q => mproc_channel_sel, q => mproc_control_registers
qmask => (0 => X"00000fff")
); );
...@@ -339,7 +341,7 @@ begin ...@@ -339,7 +341,7 @@ begin
port map( port map(
clk => clk, clk => clk,
rst => rst, rst => rst,
sel => mproc_channel_sel(0)(6 downto 0), sel => mproc_control_registers(0)(6 downto 0),
ipb_in => ipb_to_slaves(N_SLV_MPROCESSOR), ipb_in => ipb_to_slaves(N_SLV_MPROCESSOR),
ipb_out => ipb_from_slaves(N_SLV_MPROCESSOR), ipb_out => ipb_from_slaves(N_SLV_MPROCESSOR),
ipbdc_out => mprocessor_ipb_chain(0), ipbdc_out => mprocessor_ipb_chain(0),
...@@ -378,14 +380,15 @@ begin ...@@ -378,14 +380,15 @@ begin
MProcessorInstance: entity work.MProcessor MProcessorInstance: entity work.MProcessor
--==============================-- --==============================--
generic map( generic map(
N_LINKS => cNumberofInputLinks N_LINKS => cNumberofInputLinks,
INDEX => i
) )
port map( port map(
--- Input Ports --- --- Input Ports ---
clk_p => clk_p, clk_p => clk_p,
links_in => stubs(cNumberofInputLinks*i + (cNumberofInputLinks - 1) downto cNumberofInputLinks*i), links_in => stubs(cNumberofInputLinks*i + (cNumberofInputLinks - 1) downto cNumberofInputLinks*i),
header_in => header_array,
header_start_array => convertSLVtoHeaderStartArray(header_start_array_buffered), header_start_array => convertSLVtoHeaderStartArray(header_start_array_buffered),
payload_header => payload_headers(i),
gbe_backpressure => gbe_backpressure(i), gbe_backpressure => gbe_backpressure(i),
srst => srst, srst => srst,
--- Output Ports --- --- Output Ports ---
...@@ -394,10 +397,28 @@ begin ...@@ -394,10 +397,28 @@ begin
ipb_clk => clk, ipb_clk => clk,
ipb_rst => rst, ipb_rst => rst,
ipb_in => ipb_to_channel, ipb_in => ipb_to_channel,
ipb_out => ipb_from_channel ipb_out => ipb_from_channel,
--- Debug Ports ---
debug_readout_reset => readout_reset(i)
); );
end generate genMProcessors; end generate genMProcessors;
--==============================--
PayloadHeadeGeneratorInstance : entity work.PayloadHeaderGenerator
--==============================--
port map (
--- Input Ports ---
clk_p => clk_p,
reset => srst,
readout_reset => readout_reset(0),
header_start => header_start_array_buffered(0),
module_header_in => header_array,
user_bits => mproc_control_registers(1),
--- Ouput Ports ---
header_out => payload_headers
);
gbe_q <= eth_link_out; gbe_q <= eth_link_out;
q(5) <= eth_link_out(0); q(5) <= eth_link_out(0);
...@@ -443,8 +464,8 @@ begin ...@@ -443,8 +464,8 @@ begin
end if; end if;
end process; end process;
ttc_resync_reset <= mproc_channel_sel(0)(8); ttc_resync_reset <= mproc_control_registers(0)(8);
srst <= mproc_channel_sel(0)(7) or ttc_oc0; srst <= mproc_control_registers(0)(7) or ttc_oc0;
q(4).valid <= '1'; q(4).valid <= '1';
q(4).data <= "0000" & std_logic_vector(bunch_counter) & "0000000000000000" & std_logic_vector(orbit_counter); q(4).data <= "0000" & std_logic_vector(bunch_counter) & "0000000000000000" & std_logic_vector(orbit_counter);
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment