Fixed link to PF in-/output mapping

Currently we're sending the first frame of a bunch crossing to the particle flow algorithm and ignoring the remaining five frames. At a future point in time (possibly when targeting a larger chip) we can send each of the other frames to another instance of the PF IP core. Progress is tracked in #11 (closed). To fix timing the (de)multiplexer units needed to be split into quad-sized entities (tracked in #13 (closed)). Furthermore the build tools were updated (#17 (closed)) and refactoring of the HLS names was done.